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P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d,and pulse width modulator preliminary data supersedes data of 2001 aug 06 2002 mar 12 integrated circuits
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 i general description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin configuration, 20-pin dip and so packages 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic symbol 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin descriptions 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional description 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . enhanced cpu 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog functions 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog to digital converter 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a/d timing 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . the a/d in power down and idle modes 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . code examples for the a/d 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog comparators 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i2c serial interface 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupts 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/o ports 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . keyboard interrupt (kbi) 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oscillator 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power monitoring functions 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power reduction modes 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer/counters 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uart 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . watchdog timer 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . additional features 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eprom characteristics 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc electrical characteristics 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . comparator electrical characteristics 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a/d converter dc electrical characteristics 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ac electrical characteristics 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 1 2002 mar 12 general description the P87LPC768 is a 20-pin single-chip microcontroller designed for low pin count applications demanding high-integration, low cost solutions over a wide range of performance requirements. a member of the philips low pin count family, the P87LPC768 offers programmable oscillator configurations for high and low speed crystals or rc operation, wide operating voltage range, programmable port output configurations, selectable schmitt trigger inputs, led drive outputs, and a built-in watchdog timer. the P87LPC768 is based on an accelerated 80c51 processor architecture that executes instructions at twice the rate of standard 80c51 devices. features ? an accelerated 80c51 cpu provides instruction cycle times of 300600 ns for all instructions except multiply and divide when executing at 20 mhz. execution at up to 20 mhz when v dd = 4.5 v to 6.0 v, 10 mhz when v dd = 2.7 v to 6.0 v. ? four-channel 10-bit pulse width modulator ? four-channel multiplexed 8-bit a/d converter. conversion time of 9.3 m s at f osc = 20 mhz. ? 2.7 v to 6.0 v operating range for digital functions. ? 4 kbytes eprom code memory. ? 128 byte ram data memory. ? 32-byte customer code eprom allows serialization of devices, storage of setup parameters, etc. ? two 16-bit counter/timers. each timer may be configured to toggle a port output upon timer overflow. ? two analog comparators. ? full duplex uart. ? i 2 c communication port. ? eight keypad interrupt inputs, plus two additional external interrupt inputs. ? four interrupt priority levels. ? watchdog timer with separate on-chip oscillator, requiring no external components. the watchdog timeout time is selectable from 8 values. ? active low reset. on-chip power-on reset allows operation with no external reset components. ? low voltage reset. one of two preset low voltage levels may be selected to allow a graceful system shutdown when power fails. may optionally be configured as an interrupt. ? oscillator fail detect. the watchdog timer has a separate fully on-chip oscillator, allowing it to perform an oscillator fail detect function. ? configurable on-chip oscillator with frequency range and rc oscillator options (selected by user programmed eprom bits). the rc oscillator option allows operation with no external oscillator components. ? programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. ? selectable schmitt trigger port inputs. ? led drive capability (20 ma) on all port pins. ? controlled slew rate port outputs to reduce emi. outputs have approximately 10 ns minimum ramp times. ? 15 i/o pins minimum. up to 18 i/o pins using on-chip oscillator and reset options. ? only power and ground connections are required to operate the P87LPC768 when fully on-chip oscillator and reset options are selected. ? serial eprom programming allows simple in-circuit production coding. two eprom security bits prevent reading of sensitive application programs. ? idle and power down reduced power modes. improved wakeup from power down mode (a low interrupt input starts execution). typical power down current is 1 m a. ? 20-pin dip and so packages.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 2 ordering information part number temperature range c and package frequency drawing number P87LPC768bn 0 to +70, plastic dual in-line package 20 mhz (5 v), 10 mhz (3 v) sot1461 P87LPC768bd 0 to +70, plastic small outline package 20 mhz (5 v), 10 mhz (3 v) sot1631 P87LPC768fn 45 to +85, plastic dual in-line package 20 mhz (5 v), 10 mhz (3 v) sot1461 P87LPC768fd 45 to +85, plastic small outline package 20 mhz (5 v), 10 mhz (3 v) sot1631 pin configuration, 20-pin dip and so packages su01361 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 pwm3/cmp2/p0.0 pwm2/p1.7 pwm1/p1.6 rst /p1.5 v ss x1/p2.1 x2/clkout/p2.0 int1 /p1.4 sda/int0 /p1.3 scl/t0/p1.2 p0.1/cin2b/pwm0 p0.2/cin2a/brake p0.3/cin1b/ad0 p0.4/cin1a/ad1 p0.5/cmpref/ad2 v dd p0.6/cmp1/ad3 p1.0/txd p0.7/t1 p1.1/rxd 10 logic symbol t1 x1 su01362 v dd v ss txd cmp2 cin2b cin2a cin1b cin1a cmpref cmp1 clkout/x2 port 0 port 2 port 1 rxd int0 rst int1 t0 scl sda ad0 ad1 ad2 ad3 pwm3 pwm0 brake pwm1 pwm2
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 3 block diagram su01363 timer 0, 1 i 2 c uart accelerated 80c51 cpu watchdog timer and oscillator port 0 configurable i/os 128 byte data ram 4k byte code eprom internal bus analog comparators port 1 configurable i/os keypad interrupt port 2 configurable i/os power monitor (power-on reset, brownout reset) configurable oscillator crystal or resonator on-chip rc oscillator a/d converter pulse width modulator
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 4 su01386 unused code memory space 32-byte customer code space (accessible via movc) unused code memory space 4 k bytes on-chip code memory interrupt vectors special function registers (only directly addressable) 128 bytes on-chip data memory (directly and indirectly addressable) 16-bit addressable bytes unused space configuration bytes ucfg1, ucfg2 (accessible via movx) unused space ffffh fcffh fce0h 1000h 0fffh ffh 80h 7fh 0000h 00h 0000h fd00h fd01h ffffh * the P87LPC768 does not support access to external data memory. however, the user configuration bytes are accessed via the movx instruction as if they were in external data memory. on-chip code memory space on-chip data memory space external data memory space* figure 1. P87LPC768 program and data memory map
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 5 pin descriptions mnemonic pin no. type name and function p0.0p0.7 1, 13, 14, 1620 i/o port 0 : port 0 is an 8-bit i/o port with a user-configurable output type. port 0 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the prhi bit in the ucfg1 configuration byte. the operation of port 0 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. the keyboard interrupt feature operates with port 0 pins. port 0 also provides various special functions as described below. 1 o p0.0 cmp2 comparator 2 output. o pwm3 pulse width modulator 3 output. 20 i p0.1 cin2b comparator 2 positive input b. o pwm0 pulse width modulator 0 output. 19 i p0.2 cin2a comparator 2 positive input a. i brake pwm brake input. 18 i p0.3 cin1b comparator 1 positive input b. i ad0 a/d channel 0 input. 17 i p0.4 cin1a comparator 1 positive input a. i ad1 a/d channel 1 input. 16 i p0.5 cmpref comparator reference (negative) input. i ad2 a/d channel 2 input. 14 o p0.6 cmp1 comparator 1 output. i ad3 a/d channel 3 input. 13 i/o p0.7 t1 timer/counter 1 external count input or overflow output. p1.0p1.7 24, 812 i/o port 1 : port 1 is an 8-bit i/o port with a user-configurable output type, except for three pins as noted below. port 1 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the prhi bit in the ucfg1 configuration byte. the operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected. each of the configurable port pins are programmed independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. port 1 also provides various special functions as described below. 12 o p1.0 txd transmitter output for the serial port. 11 i p1.1 rxd receiver input for the serial port. 10 i/o i/o p1.2 t0 timer/counter 0 external count input or overflow output. scl i 2 c serial clock input/output. when configured as an output, p1.2 is open drain, in order to conform to i 2 c specifications. 9 i i/o p1.3 int0 external interrupt 0 input. sda i 2 c serial data input/output. when configured as an output, p1.3 is open drain, in order to conform to i 2 c specifications. 8 i p1.4 int1 external interrupt 1 input. 4 i p1.5 rst external reset input (if selected via eprom configuration). a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. when used as a port pin, p1.5 is a schmitt trigger input only. 3 o p1.6 pwm1 pulse width modulator 1 output 2 o p1.7 pwm2 pulse width modulator 2 output
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 6 mnemonic name and function type pin no. p2.0p2.1 6, 7 i/o port 2 : port 2 is a 2-bit i/o port with a user-configurable output type. port 2 latches are configured in the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by the prhi bit in the ucfg1 configuration byte. the operation of port 2 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to the section on i/o port configuration and the dc electrical characteristics for details. port 2 also provides various special functions as described below. 7 o p2.0 x2 output from the oscillator amplifier (when a crystal oscillator option is selected via the eprom configuration). clkout cpu clock divided by 6 clock output when enabled via sfr bit and in conjunction with internal rc oscillator or external clock input. 6 i p2.1 x1 input to the oscillator circuit and internal clock generator circuits (when selected via the eprom configuration). v ss 5 i ground : 0v reference. v dd 15 i power supply : this is the power supply voltage for normal operation as well as idle and power down modes.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 7 special function registers name description sfr address bit functions and addresses msb lsb reset value e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00h c7 c6 c5 c4 c3 c2 c1 c0 adcon#* a/d control c0h enadc adci adcs rcclk aadr1 aadr0 00h auxr1# auxiliary function register a2h kbf bod boi lpep srst 0 dps 02h 1 f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00h cmp1# comparator 1 control register ach ce1 cp1 cn1 oe1 co1 cmf1 00h 1 cmp2# comparator 2 control register adh ce2 cp2 cn2 oe2 co2 cmf2 00h 1 cnsw0 pwm counter shadow register 0 d1h cnsw7 cnsw6 cnsw5 cnsw4 cnsw3 cnsw2 cnsw1 cnsw0 ffh cnsw1 pwm counter shadow register 1 d2h cnsw9 cnsw8 ffh cpsw0 pwm compare shadow register 0 d3h cpsw07 cpsw06 cpsw05 cpsw04 cpsw03 cpsw02 cpsw01 cpsw00 00h cpsw1 pwm compare shadow register 1 d4h cpsw17 cpsw16 cpsw15 cpsw14 cpsw13 cpsw12 cpsw11 cpsw10 00h cpsw2 pwm compare shadow register 2 d5h cpsw27 cpsw26 cpsw25 cpsw24 cpsw23 cpsw22 cpsw21 cpsw20 00h cpsw3 pwm compare shadow register 3 d6h cpsw37 cpsw36 cpsw35 cpsw34 cpsw33 cpsw32 cpsw31 cpsw30 00h cpsw4 pwm compare shadow register 4 d7h cpsw39 cpsw38 cpsw29 cpsw28 cpsw19 cpsw18 cpsw09 cpsw08 00h dac0# a/d result c5h 00h divm# cpu clock divide-by-m control 95h 00h dptr: data pointer (2 bytes) dph data pointer high byte 83h 00h dpl data pointer low byte 82h 00h cf ce cd cc cb ca c9 c8 i2cfg#* i 2 c configuration register c8h/rd slaven mastrq 0 tirun ct1 ct0 00h 1 c8h/wr slaven mastrq clrti tirun ct1 ct0 df de dd dc db da d9 d8 i2con#* i 2 c control register d8h/rd rdat atn drdy arl str stp master 80h 1 d8h/wr cxa idle cdr carl cstr cstp xstr xstp i2dat# i 2 c data register d9h/rd rdat 0 0 0 0 0 0 0 80h d9h/wr xdat x x x x x x x af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewd ebo es et1 ex1 et0 ex0 00h ef ee ed ec eb ea e9 e8 ien1#* interrupt enable 1 e8h eti ec1 ead ec2 ekb ei2 00h 1 bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h pwd pbo ps pt1 px1 pt0 px0 00h 1 ip0h# interrupt priority 0 high byte b7h pwdh pboh psh pt1h px1h pt0h px0h 00h 1 ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h pti pc1 pad pc2 pkb pi2 00h 1 ip1h# interrupt priority 1 high byte f7h ptih pc1h padh pc2h pkbh pi2h 00h 1
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 8 name reset value bit functions and addresses msb lsb sfr address description kbi# keyboard interrupt 86h 00h 87 86 85 84 83 82 81 80 p0* port 0 80h t1 cmp1 cmpref cin1a cin1b cin2a cin2b cmp2 note 2 97 96 95 94 93 92 91 90 p1* port 1 90h (p1.7) (p1.6) rst int1 int0 t0 rxd txd note 2 a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h x1 x2 note 2 p0m1# port 0 output mode 1 84h (p0m1.7) (p0m1.6) (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) (p0m1.0) 00h p0m2# port 0 output mode 2 85h (p0m2.7) (p0m2.6) (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) (p0m2.0) 00h p1m1# port 1 output mode 1 91h (p1m1.7) (p1m1.6) (p1m1.4) (p1m1.1) (p1m1.0) 00h 1 p1m2# port 1 output mode 2 92h (p1m2.7) (p1m2.6) (p1m2.4) (p1m2.1) (p1m2.0) 00h 1 p2m1# port 2 output mode 1 a4h p2s p1s p0s enclk t1oe t0oe (p2m1.1) (p2m1.0) 00h p2m2# port 2 output mode 2 a5h (p2m2.1) (p2m2.0) 00h 1 pcon power control register 87h smod1 smod0 bof pof gf1 gf0 pd idl note 3 d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h pt0ad# port 0 digital input disable f6h 00h 9f 9e 9d 9c 9b 9a 99 98 pwmcon0 pwm control register 0 dah run xfer pwm3i pwm2i pwm1i pwm0i 00h pwmcon1 pwm control register 1 dbh bkch bkps bpen bken pwm3b pwm2b pwm1b pwm0b 00h scon* serial port control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sbuf serial port data buffer register 99h xxh saddr# serial port address register a9h 00h saden# serial port address enable b9h 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer 0 high byte 8ch 00h th1 timer 1 high byte 8dh 00h tl0 timer 0 low byte 8ah 00h tl1 timer 1 low byte 8bh 00h tmod timer 0 and 1 mode 89h gate c/t m1 m0 gate c/t m1 m0 00h wdcon# watchdog control register a7h wdovf wdrun wdclk wds2 wds1 wds0 note 4 wdrst# watchdog reset register a6h xxh notes: * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. 1. unimplemented bits in sfrs are x (unknown) at all times. ones should not be written to these bits since they may be used for other purposes in future derivatives. the reset value shown in the table for these bits is 0. 2. i/o port values at reset are determined by the prhi bit in the ucfg1 configuration byte. 3. the pcon reset value is x x bof pof0 0 0 0b. the bof and pof flags are not affected by reset. the pof flag is set by hardwar e upon power up. the bof flag is set by the occurrence of a brownout reset/interrupt and upon power up. 4. the wdcon reset value is xx11 0000b for a watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, a nd xx00 0000b for all other reset causes if the watchdog is disabled.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 9 functional description details of P87LPC768 functions will be described in the following sections. enhanced cpu the P87LPC768 uses an enhanced 80c51 cpu which runs at twice the speed of standard 80c51 devices. this means that the performance of the P87LPC768 running at 5 mhz is exactly the same as that of a standard 80c51 running at 10 mhz. a machine cycle consists of 6 oscillator cycles, and most instructions execute in 6 or 12 clocks. a user configurable option allows restoring standard 80c51 execution timing. in that case, a machine cycle becomes 12 oscillator cycles. in the following sections, the term acpu clocko is used to refer to the clock that controls internal instruction execution. this may sometimes be different from the externally applied clock, as in the case where the part is configured for standard 80c51 timing by means of the clkr configuration bit or in the case where the clock is divided down via the setting of the divm register. these features are described in the oscillator section. analog functions the P87LPC768 incorporates analog peripheral functions: an analog to digital converter and two analog comparators. in order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and inputs disabled. digital outputs are disabled by putting the port output into the input only (high impedance) mode as described in the i/o ports section. digital inputs on port 0 may be disabled through the use of the pt0ad register. each bit in this register corresponds to one pin of port 0. setting the corresponding bit in pt0ad disables that pin's digital input. port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port. analog to digital converter the P87LPC768 incorporates a four channel, 8-bit a/d converter. the a/d inputs are alternate functions on four port 0 pins. because the device has a very limited number of pins, the a/d power supply and references are shared with the processor power pins, v dd and v ss . the a/d converter operates down to a v dd supply of 3.0v. the a/d converter circuitry consists of a 4-input analog multiplexer and an 8-bit successive approximation adc. the a/d employs a ratiometric potentiometer which guarantees dac monotonicity. the a/d converter is controlled by the special function register adcon. details of adcon are shown in figure 2. the a/d must be enabled by setting the enadc bit at least 10 microseconds before a conversion is started, to allow time for the a/d to stabilize. prior to the beginning of an a/d conversion, one analog input pin must be selected for conversion via the aadr1 and aadr0 bits. these bits cannot be changed while the a/d is performing a conversion. an a/d conversion is started by setting the adcs bit, which remains set while the conversion is in progress. when the conversion is complete, the adcs bit is cleared and the adci bit is set. when adci is set, it will generate an interrupt if the interrupt system is enabled, the a/d interrupt is enabled (via the ead bit in the ie1 register), and the a/d interrupt is the highest priority pending interrupt. when a conversion is complete, the result is contained in the register dac0. this value will not change until another conversion is started. before another a/d conversion may be started, the adci bit must be cleared by software. the a/d channel selection may be changed by the same instruction that sets adcs to start a new conversion, but not by the same instruction that clears adci. the connections of the a/d converter are shown in figure 3. the ideal a/d result may be calculated as follows: result (v in v ss )x 256 v dd v ss (round result to the nearest integer)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 10 adcon address: c0h bit addressable reset value: 00h bit symbol function adcon.7 enadc when enadc = 1, the a/d is enabled and conversions may take place. must be set 10 microseconds before a conversion is started. enadc cannot be cleared while adcs or adci are 1. adcon.6 - reserved for future use. should not be set to 1 by user programs. adcon.5 - reserved for future use. should not be set to 1 by user programs. adcon.4 adci a/d conversion complete/interrupt flag. this flag is set when an a/d conversion is completed. this bit will cause a hardware interrupt if enabled and of sufficient priority. must be cleared by software. adcon.3 adcs a/d start. setting this bit by software starts the conversion of the selected a/d input. adcs remains set while the a/d conversion is in progress and is cleared automatically upon completion. while adcs or adci are one, new start commands are ignored. adci, adcs a/d status 0 0 a/d not busy, a conversion can be started. 0 1 a/d busy, the start of a new conversion is blocked. 1 0 an a/d conversion is complete. adci must be cleared prior to starting a new conversion. 1 1 an a/d conversion is complete. adci must be cleared prior to starting a new conversion. this state exists for one machine cycle as an a/d conversion is completed. adcon.2 rcclk when rcclk = 0, the cpu clock is used as the a/d clock. when rcclk = 1, the internal rc oscillator is used as the a/d clock. this bit is writable while adcs and adci are 0. adcon.1, 0 aadr1,0 along with aadr0, selects the a/d channel to be converted. these bits can only be written while adcs and adci are 0. aadr1, aadr0 a/d input selected 0 0 ad0 (p0.3). 0 1 ad1 (p0.4). 1 0 ad2 (p0.5). 1 1 ad3 (p0.6). 76543210 enadc - - adci adcs rcclk aadr1 aadr0 su01354 figure 2. a/d control register (adcon) a/d timing the a/d may be clocked in one of two ways. the default is to use the cpu clock as the a/d clock source. when used in this manner, the a/d completes a conversion in 31 machine cycles. the a/d may be operated up to the maximum cpu clock rate of 20 mhz, giving a conversion time of 9.3 m s. the formula for calculating a/d conversion time when the cpu clock runs the a/d is: 186 m s / cpu clock rate (in mhz). to obtain accurate a/d conversion results, the cpu clock must be at least 1 mhz. the a/d may also be clocked by the on-chip rc oscillator, even if the rc oscillator is not used as the cpu clock. this is accomplished by setting the rcclk bit in adcon. this arrangement has several advantages. first, the a/d conversion time is faster at lower cpu clock rates. also, the cpu may be run at speeds below 1 mhz without affecting a/d accuracy. finally, the power down mode may be used to completely shut down the cpu and its oscillator, along with other peripheral functions, in order to obtain the best possible a/d accuracy. this should not be used if the mcu uses an external clock source greater than 4 mhz. when the a/d is operated from the rcclk while the cpu is running from another clock source, 3 or 4 machine cycles are used to synchronize a/d operation. the time can range from a minimum of 3 machine cycles (at the cpu clock rate) + 108 rc clocks to a maximum of 4 machine cycles (at the cpu clock rate) + 112 rc clocks. example a/d conversion times at various cpu clock rates are shown in table 1. in table 1, maximum times for rcclk = 1 use an rc clock frequency of 4.5 mhz (6 mhz - 25%). minimum times for rcclk = 1 use an rc clock frequency of 7.5 mhz (6 mhz + 25%). nominal time assume an ideal rc clock frequency of 6 mhz and an average of 3.5 machine cycles at the cpu clock rate.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 11 table 1. example a/d conversion times cpu clock rate rcclk = 0 rcclk = 1 cpu clock rate rcclk = 0 minimum nominal maximum 32 khz na 563.4 m s 659 m s 757 m s 1 mhz 186 m s 32.4 m s 39.3 m s 48.9 m s 4 mhz 46.5 m s 18.9 m s 23.6 m s 30.1 m s 11.0592 mhz 16.8 m s 16 m s 20.2 m s 27.1 m s 12 mhz 15.5 m s 16 mhz 11.6 m s 20 mhz 9.3 m s note: do not clock adc from the rc oscillator when mcu clock is greater than 4 mhz. ad0 (p0.3) ad1 (p0.4) v ref + = v dd aadr1 ad2 (p0.5) ad3 (p0.6) 00 01 10 11 v ref - = v ss adcon a/d converter aadr0 dac0 (a/d result) su01356 figure 3. a/d converter connections the a/d in power down and idle modes while using the cpu clock as the a/d clock source, the idle mode may be used to conserve power and/or to minimize system noise during the conversion. cpu operation will resume and idle mode terminate automatically when a conversion is complete if the a/d interrupt is active. in idle mode, noise from the cpu itself is eliminated, but noise from the oscillator and any other on-chip peripherals that are running will remain. the cpu may be put into power down mode when the a/d is clocked by the on-chip rc oscillator (rcclk=1). this mode gives the best possible a/d accuracy by eliminating most on-chip noise sources. if the power down mode is entered while the a/d is running from the cpu clock (rcclk=0), the a/d will abort operation and will not wake up the cpu. the contents of dac0 will be invalid when operation does resume. when an a/d conversion is started, power down or idle mode must be activated within two machine cycles in order to have the most accurate a/d result. these two machine cycles are counted at the cpu clock rate. when using the a/d with either power down or idle mode, care must be taken to insure that the cpu is not restarted by another interrupt until the a/d conversion is complete. the possible causes of wakeup are different in power down and idle modes. a/d accuracy is also affected by noise generated elsewhere in the application, power supply noise, and power supply regulation. since the P87LPC768 power pins are also used as the a/d reference and supply, the power supply has a very direct affect on the accuracy of a/d readings. using the a/d without power down mode while the clock is divided through the use of clkr or divm has an adverse effect on a/d accuracy.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 12 code examples for the a/d the first piece of sample code shows an example of port configuration for use with the a/d. this example sets up the pins so th at all four a/d channels may be used. port configuration for analog functions is described in the section analog functions. ; set up port pins for a/d conversion, without affecting other pins. mov pt0ad,#78h ; disable digital inputs on a/d input pins. anl p0m2,#87h ; disable digital outputs on a/d input pins. orl p0m1,#78h ; disable digital outputs on a/d input pins. following is an example of using the a/d with interrupts. the routine adstart begins an a/d conversion using the a/d channel nu mber supplied in the accumulator. the channel number is not checked for validity. the a/d must previously have been enabled with sufficient t ime to allow for stabilization. the interrupt handler routine reads the conversion value and returns it in memory address adresult. the interrupt should be ena bled prior to starting the conversion. ; start a/d conversion. adstart: orl adcon,a ; add in the new channel number. setb adcs ; start an a/d conversion. ; orl pcon,#01h ; the cpu could be put into idle mode here. ; orl pcon,#02h ; the cpu could be put into power down mode here if rcclk = 1. ret ; a/d interrupt handler. adint: push acc ; save accumulator. mov a,dac0 ; get a/d result, mov adresult,a ; and save it in memory. clr adci ; clear the a/d completion flag. anl adcon,#0fch ; clear the a/d channel number. pop acc ; restore accumulator. reti following is an example of using the a/d with polling. an a/d conversion is started using the channel number supplied in the ac cumulator. the channel number is not checked for validity. the a/d must previously have been enabled with sufficient time to allow for stabili zation. the conversion result is returned in the accumulator. adread: orl adcon,a ; add in the new channel number. setb adcs ; start a/d conversion. adchk: jnb adci,adchk ; wait for adci to be set. mov a,dac0 ; get a/d result. clr adci ; clear the a/d completion flag. anl adcon,#0fch ; clear the a/d channel number. ret
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 13 analog comparators two analog comparators are provided on the P87LPC768. input and output options allow use of the comparators in a number of different configurations. comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). otherwise the output is a zero. each comparator may be configured to cause an interrupt when the output value changes. comparator configuration each comparator has a control register, cmp1 for comparator 1 and cmp2 for comparator 2. the control registers are identical and are shown in figure 4. the overall connections to both comparators are shown in figure 5. there are eight possible configurations for each comparator, as determined by the control bits in the corresponding cmpn register: cpn, cnn, and oen. these configurations are shown in figure 6. the comparators function down to a v dd of 3.0v. when each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. the corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. bit symbol function cmpn.7, 6 e reserved for future use. should not be set to 1 by user programs. cmpn.5 cen comparator enable. when set by software, the corresponding comparator function is enabled. comparator output is stable 10 microseconds after cen is first set. cmpn.4 cpn comparator positive input select. when 0, cinna is selected as the positive comparator input. when 1, cinnb is selected as the positive comparator input. cmpn.3 cnn comparator negative input select. when 0, the comparator reference pin cmpref is selected as the negative comparator input. when 1, the internal comparator reference v ref is selected as the negative comparator input. cmpn.2 oen output enable. when 1, the comparator output is connected to the cmpn pin if the comparator is enabled (cen = 1). this output is asynchronous to the cpu clock. cmpn.1 con comparator output, synchronized to the cpu clock to allow reading by software. cleared when the comparator is disabled (cen = 0). cmpn.0 cmfn comparator interrupt flag. this bit is set by hardware whenever the comparator output con changes state. this bit will cause a hardware interrupt if enabled and of sufficient priority. cleared by software and when the comparator is disabled (cen = 0). cmfn su01152 con oen cnn cpn cen e e 0 1 2 3 4 5 6 7 cmpn reset value: 00h not bit addressable address: ach for cmp1, adh for cmp2 figure 4. comparator control registers (cmp1 and cmp2)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 14 su01153 + (p0.4) cin1a comparator 1 (p0.3) cin1b co1 oe1 (p0.5) cmpref + (p0.2) cin2a comparator 2 (p0.1) cin2b co2 oe2 cp1 cn1 cp2 cn2 cmp2 (p0.0) cmp1 (p0.6) change detect cmf1 interrupt change detect cmf2 interrupt v ref figure 5. comparator input and output connections v ref (1.23v) v ref (1.23v) v ref (1.23v) su01154 + cinna cmpref con cpn, cnn, oen = 0 0 0 + cinna cmpref cmpn con cpn, cnn, oen = 0 0 1 + cinna cmpn con cpn, cnn, oen = 0 1 1 + cinnb cmpref cmpn con cpn, cnn, oen = 1 0 1 + cinnb cmpn con cpn, cnn, oen = 1 1 1 cpn, cnn, oen = 0 1 0 cpn, cnn, oen = 1 0 0 cpn, cnn, oen = 1 1 0 + cinna vref (1.23v) con + cinnb cmpref con + cinnb con figure 6. comparator configurations
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 15 internal reference voltage an internal reference voltage generator may supply a default reference when a single comparator input pin is used. the value of the internal reference voltage, referred to as v ref , is 1.28 v 10%. comparator interrupt each comparator has an interrupt flag cmfn contained in its configuration register. this flag is set whenever the comparator output changes state. the flag may be polled by software or may be used to generate an interrupt. the interrupt will be generated when the corresponding enable bit ecn in the ien1 register is set and the interrupt system is enabled via the ea bit in the ien0 register. comparators and power reduction modes either or both comparators may remain enabled when power down or idle mode is activated. the comparators will continue to function in the power reduction mode. if a comparator interrupt is enabled, a change of the comparator output state will generate an interrupt and wake up the processor. if the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in power down mode. the reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. comparators consume power in power down and idle modes, as well as in the normal operating mode. this fact should be taken into account when system power consumption is an issue. comparator configuration example the code shown in figure 7 is an example of initializing one comparator. comparator 1 is configured to use the cin1a and cmpref inputs, outputs the comparator result to the cmp1 pin, and generates an interrupt when the comparator output changes. the interrupt routine used for the comparator must clear the interrupt flag (cmf1 in this case) before returning. su01189 cmpinit: mov pt0ad,#30h ; disable digital inputs on pins that are used ; for analog functions: cin1a, cmpref. anl p0m2,#0cfh ; disable digital outputs on pins that are used orl p0m1,#30h ; for analog functions: cin1a, cmpref. mov cmp1,#24h ; turn on comparator 1 and set up for: ; positive input on cin1a. ; negative input from cmpref pin. ; output to cmp1 pin enabled. call delay10us ; the comparator has to start up for at ; least 10 microseconds before use. anl cmp1,#0feh ; clear comparator 1 interrupt flag. setb ec1 ; enable the comparator 1 interrupt. the ; priority is left at the current value. setb ea ; enable the interrupt system (if needed). ret ; return to caller. figure 7. pulse width modulator the P87LPC768 contains four pulse width modulated (pwm) channels which generate pulses of programmable length and interval. the output for pwm0 is on p0.1, pwm1 on p1.6, pwm2 on p1.7 and pwm3 on p0.0. after chip reset the internal output of the each pwm channel is a a1.o note that the state of the pin will not reflect this if ucfg1.5, prhi, is set to a zero. in this case before the pin will reflect the state of the internal pwm output a a1o must be written to each port bit that serves as a pwm output. a block diagram is shown in figure 8. the interval between successive outputs is controlled by a 10bit down counter which uses the internal microcontroller clock as its input. when bit 3 in the ucfg1 register is a a1o the microcontroller clock, and therefore the pwm counter clock, has the same frequency as the clock source f cpwm = f osc . when bit 3 in the ucfg1 register is a a0o the microcontroller and pwm counter clocks operate at half the frequency of clock source, f cpwm = f osc /2. when the counter reaches underflow it is reloaded with a user selectable value. this mechanism allows the user to set the pwm frequency at any integer submultiple of the microcontroller clock frequency. the repetition frequency of the pwm is given by: f pwm = f cpwm / (cnsw+1) where cnsw is contained in cnsw0 and cnsw1 as described in the following tables.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 16 cnsw0: counter shadow register 0 addr: 0d1h reset value: ffh 76543210 cnsw7 cnsw6 cnsw5 cnsw4 cnsw3 cnsw2 cnsw1 cnsw0 cnsw1: counter shadow register 1 addr: 0d2h reset value: ffh 76 5 432 1 0 unused unused unused unused unused unused cnsw9 cnsw8 the word ashadowo in the above refers to the fact that writes are not into the register that controls the counter; rather they are into a holding register. as described below the transfer of data from this holding register, into the register which contains the actual reload value, is controlled by the user's program. internal bus 10 bit shadow register 10 bit counter register 10 bit shadow register 10 bit compare register 10 bit shadow register 10 bit compare register 10 bit shadow register 10 bit compare register 10 bit shadow register 10 bit compare register 10 bit counter a>b a>b a>b a>b run xfer brake bkch bkps bpen bken brake control logic 2:1 mux pwm3i pwm3b pwm3 2:1 mux pwm2i pwm2b pwm2 2:1 mux pwm1i pwm1b pwm1 2:1 mux pwm0i pwm0b pwm0 ab ab ab ab su01364 figure 8. pwm block diagram
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 17 the width of each pwm output pulse is determined by the value in the appropriate compare shadow registers, cpsw0 through cpsw4, cpsw03 for bits 07 and cpsw4 for bits 7 and 8. when the counter described above reaches underflow the pwm output is forced high. it remains high until the compare value is reached at which point it goes low until the next underflow. the number of microcontroller clock pulses that the pwm n output is high is given by: t hi = (cnsw cpsw n +1) a compare value greater than the counter reload value results in the pwm output being permanently high. in addition there are two special cases. a compare value of all zeroes, 000, causes the output to remain permanently high. a compare value of all ones, 3ff, results in the pwm output remaining permanently low. again the compare value is loaded into a shadow register. the transfer from this holding register to the actual compare register is under program control. the register assignments are shown below where the number immediately following acpswo identifies the pwm output. thus cpsw0 controls the width of pwm0, cpsw1 the width of pwm1 etc. in the case of two digits following acpsw,o e.g. cpsw00, the second digit refers to the bit of the compare value. thus cpsw00 represents the value loaded into bit 0 of the pwm0 compare register cpsw0: compare shadow register 0 addr: 0d3h reset value: 00h 765432 1 0 cpsw07 cpsw06 cpsw05 cpsw04 cpsw03 cpsw02 cpsw01 cpsw00 cpsw1: compare shadow register 1 addr: 0d4h reset value: 00h 765432 1 0 cpsw17 cpsw16 cpsw15 cpsw14 cpsw13 cpsw12 cpsw11 cpsw10 cpsw2: compare shadow register 2 addr: 0d5h reset value: 00h 765432 1 0 cpsw27 cpsw26 cpsw25 cpsw24 cpsw23 cpsw22 cpsw21 cpsw20 cpsw3: compare shadow register 3 addr: 0d6h reset value: 00h 765432 1 0 cpsw37 cpsw36 cpsw35 cpsw34 cpsw33 cpsw32 cpsw31 cpsw30 cpsw4: compare shadow register 4 addr: 0d7h reset value: 00h 765432 1 0 cpsw39 cpsw38 cpsw29 cpsw28 cpsw19 cpsw18 cpsw09 cpsw08 the overall functioning of the pwm module is controlled by the contents of the pwmcon0 register. the operation of most of the control bits is straightforward. for example there is an invert bit for each output which causes results in the output to have the opposite value compared to its non-inverted output. the transfer of the data from the shadow registers to the control registers is controlled by the pwmcon0.6 while pwmcon0.7 allows the pwm to be either in the run or idle state. the user can monitor when underflow causes the transfer to occur by monitoring the transfer bit, pwcon0.6. when the transfer takes place the pwm logic automatically resets this bit. the fact that the transfer from the shadow to the working registers only occurs when there is an underflow in the counter results in the need for the user's program to observe the following precautions. if pwmcon1 is written with transfer set without run being enabled the transfer will never take place. thus if a subsequent write sets run without transfer the compare and counter values will not be those expected. if transfer and run are set, and prior to underflow there is a subsequent load of pwmcon0 which sets run but not transfer, the transfer will never take place. again the compare and counter values that existed prior to the update attempt will be used. as outlined above the transfer bit can be polled to determine when the transfer occurs. unless there is a compelling reason to do otherwise, it is recommended that both run, pwmcon0.7, and transfer, pwmcon0.7, be set when pwmcon0 is written. when the run bit, pwmcon0.7, is cleared the pwm outputs take on the state they had just prior to the bit being cleared. in general this state is not known. in order to place the outputs in a known
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 18 state when run is cleared the compare registers can be written to either the aalways 1o or aalways 0o so the output will have the output desired when the counter is halted. after this pwmcon0 should be written with the transfer and run bits are enabled. after this is done pwmcon0 to is polled to find that the transfer has taken place. once the transfer has occurred the run bit in pwmcon0 can be cleared. the outputs will retain the state they had just prior to the run being cleared. if the brake pin (see discussion below in section concerning the operation of pwmcon1) is not used to control the brake function, the abrake when not runningo function can be used to cause the outputs to have a given state when the pwm is halted. this approach should be used only in time critical situations when there is not sufficient time to use the approach outlined above since going from the brake state to run without causing an undefined state on the outputs is not straightforward. a discussion on this topic is included in the section on pwmcon1. pwmcon0: pwm control register 0 addr: 0dah reset value: 00h bit symbol function pwmcon0.7 run 0= counter halted & preset value loaded. if brake is asserted, pwmx output will be equal to the value of the corresponding pwmxb bit (pwmcon1[3:0]). if brake is not asserted, pwmx output will be equal to the value after compare 1= counter run pwmcon0.6 xfer 0= counter & compare shadow registers are not connected to the active registers 1= shadow register contents transferred to active registers, at the next counter underflow this bit is autocleared by hardware after the data transfer from shadow to active registers pwmcon0.5 pwm3i 0= pwm3 output is noninverted. output is a `1' from the start of the cycle until compare; '0' thereafter. 1= pwm3 output is inverted. output is a `0' from the start of the cycle until compare; '0' thereafter. pwmcon0.4 pwm2i 0= pwm2 output is noninverted. output is a `1' from the start of the cycle until compare; '0' thereafter. 1= pwm2 output is inverted. output is `0' from the start of the cycle until compare; '1' thereafter. pwmcon0.2 pwm1i 0= pwm1 output is noninverted. output is a `1' from the start of the cycle until compare; '0' thereafter. 1= pwm1 output is inverted. output is `0' from the start of the cycle until compare; '1' thereafter. pwmcon0.1 pwm0i 0= pwm0 output is noninverted. output is a `1' from the start of the cycle until compare; '0' thereafter. 1= pwm0 output is inverted. output is `0' from the start of the cycle until compare; '1' thereafter. 76543210 run xfer pwm3i pwm2i pwm1i pwm0i su01387 the brake function, which is controlled by the contents of the pwmcon1 register, is somewhat unique. in general when brake is asserted the four pwm outputs are forced to a user selected state, namely the state selected by pwmcon1 bits 0 to 3. as shown in the description of the operation of the pwmcon1 register if pwmcon1.4 is a a1o brake is asserted under the control pwmcon1.7, bkch, and pwmcon1.5, bpen. as shown if both are a a0o brake is asserted. if pwmcon1.7 is a a1o brake is asserted when the run bit, pwmcon0.7, is a a0.o if pwmcon1.6 is a a1o brake is asserted when the brake pin, p0.2, has the same polarity as pwmcon1.6. when brake is asserted in response to this pin the run bit, pwmcon0.7, is automatically cleared. the combination of both pwmcon1.7 and pwmcon1.5 being a a1o is not allowed. since the brake pin being asserted will automatically clear the run bit, pwmcon0.7, the user program can poll this bit to determine when the brake pin causes a brake to occur. the other method for detecting a brake caused by the brake pin would be to tie the brake pin to one of the external interrupt pins. this latter approach is needed if the brake signal can be of insufficient length to ensure that it can be captured by a polling routine. when, after being asserted, the condition causing the brake is removed, the pwm outputs go to whatever state that had immediately prior to the brake. this means that in order to go from brake being asserted to having the pwm run without going through an indeterminate state care must be taken. if the brake pin causes brake to be asserted the following prototype code will allow the pwm to go from brake to run smoothly. ? rewrite pwmcon1 to change from brake pin enabled to s/w brake ? write cpsw.(0:4) to always a1o, 11 h, or always a0o 00 h, to give brake pattern ? set pwmcon0 to enable run and transfer. ? poll brake pin until it is no longer active. when no longer active:
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 19 ? poll pwmcon0 to find that transfer bit pwmcon0.6 is a0o. when a0o: ? write cnsw.(0:1) and cpsw.(0:4) for desired pulse widths and counter reload values ? set pwmcon0 to run and transfer note that if a narrow pulse on the brake pin causes brake to be asserted, it may not be possible to go through the above code before the end of the pulse. in this case, in addition to the code shown, an external latch on the brake pin may be required to ensure that there is a smooth transition in going from brake to run. the details for pwmcon1 are shown in the following table. pwmcon1: pwm control register 1 addr: 0dbh reset value: 00h bit symbol function pwmcon1.7 bkch see table below pwmcon1.6 bkps 0= obrakeo is asserted if p0.2(brake pin) is low. 1= obrakeo is asserted if p0.2(brake pin) is high. pwmcon1.5 bpen see table below. pwmcon1.4 bken 0= obrakeo is never asserted. 1= obrakeo is enabled per table below. pwmcon1.3 pwm3b 0= pwm3 is low, when brake is asserted. 1= pwm3 is high, when brake is asserted. pwmcon1.2 pwm2b 0= pwm2 is low, when brake is asserted. 1= pwm2 is high, when brake is asserted. pwmcon1.1 pwm1b 0= pwm1 is low, when brake is asserted. 1= pwm1 is high, when brake is asserted. pwmcon1.0 pwm0b 0= pwm0 is low, when brake is asserted. 1= pwm0 is high, when brake is asserted. 76543210 bkch bkps bpen bken pwm3b pwm2b pwm1b pwm0b su01388 bpen 0 0 1 1 bkch 0 1 0 1 brake condition always on, (software brake) on when pwm not running (brake pin has no effect) on when brake pin asserted (pwm run has no effect) not allowed
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 20 i 2 c serial interface the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: ? bidirectional data transfer between masters and slaves. ? serial addressing of slaves (no added wiring). ? acknowledgment after each transferred byte. ? multimaster bus. ? arbitration between simultaneously transmitting masters without corruption of serial data on bus. the i 2 c subsystem includes hardware to simplify the software required to drive the i 2 c bus. the hardware is a single bit interface which in addition to including the necessary arbitration and framing error checks, includes clock stretching and a bus timeout timer. the interface is synchronized to software either through polled loops or interrupts. refer to the application note an422, entitled ausing the 8xc751 microcontroller as an i 2 c bus mastero for additional discussion of the 8xc76x i 2 c interface and sample driver routines. the P87LPC768 i2c implementation duplicates that of the 87c751 and 87c752 except for the following details: ? the interrupt vector addresses for both the i 2 c interrupt and the timer i interrupt. ? the i 2 c sfr addresses (i2con, !2cfg, i2dat). ? the location of the i 2 c interrupt enable bit and the name of the sfr it is located within (ei2 is bit 0 in ien1). ? the location of the timer i interrupt enable bit and the name of the sfr it is located within (eti is bit 7 in ien1). ? the i 2 c and timer i interrupts have a settable priority. timer i is used to both control the timing of the i 2 c bus and also to detect a abus lockedo condition, by causing an interrupt when nothing happens on the i 2 c bus for an inordinately long period of time while a transmission is in progress. if this interrupt occurs, the program has the opportunity to attempt to correct the fault and resume i 2 c operation. six time spans are important in i 2 c operation and are insured by timer i: ? the minimum high time for scl when this device is the master. ? the minimum low time for scl when this device is a master. this is not very important for a single-bit hardware interface like this one, because the scl low time is stretched until the software responds to the i 2 c flags. the software response time normally meets or exceeds the min lo time. in cases where the software responds within min hi + min lo) time, timer i will ensure that the minimum time is met. ? the minimum scl high to sda high time in a stop condition. ? the minimum sda high to sda low time between i 2 c stop and start conditions (4.7ms, see i 2 c specification). ? the minimum sda low to scl low time in a start condition. ? the maximum scl change time while an i 2 c frame is in progress. a frame is in progress between a start condition and the following stop condition. this time span serves to detect a lack of software response on this device as well as external i 2 c problems. scl astuck lowo indicates a faulty master or slave. scl astuck higho may mean a faulty device, or that noise induced onto the i 2 c bus caused all masters to withdraw from i 2 c arbitration. the first five of these times are 4.7 ms (see i 2 c specification) and are covered by the low order three bits of timer i. timer i is clocked by the P87LPC768 cpu clock. timer i can be pre-loaded with one of four values to optimize timing for different oscillator frequencies. at lower frequencies, software response time is increased and will degrade maximum performance of the i 2 c bus. see special function register i2cfg description for prescale values (ct0, ct1). the maximum scl change time is important, but its exact span is not critical. the complete 10 bits of timer i are used to count out the maximum time. when i 2 c operation is enabled, this counter is cleared by transitions on the scl pin. the timer does not run between i 2 c frames (i.e., whenever reset or stop occurred more recently than the last start). when this counter is running, it will carry out after 1020 to 1023 machine cycles have elapsed since a change on scl. a carry out causes a hardware reset of the i 2 c interface and generates an interrupt if the timer i interrupt is enabled. in cases where the bus hang-up is due to a lack of software response by this device, the reset releases scl and allows i 2 c operation among other devices to continue. timer i is enabled to run, and will reset the i 2 c interface upon overflow, if the tirun bit in the i2cfg register is set. the timer i interrupt may be enabled via the eti bit in ien1, and its priority set by the ptih and pti bits in the ip1h and ip1 registers respectively. i 2 c interrupts if i 2 c interrupts are enabled (ea and ei2 are both set to 1), an i 2 c interrupt will occur whenever the atn flag is set by a start, stop, arbitration loss, or data ready condition (refer to the description of atn following). in practice, it is not efficient to operate the i 2 c interface in this fashion because the i 2 c interrupt service routine would somehow have to distinguish between hundreds of possible conditions. also, since i 2 c can operate at a fairly high rate, the software may execute faster if the code simply waits for the i 2 c interface. typically, the i 2 c interrupt should only be used to indicate a start condition at an idle slave device, or a stop condition at an idle master device (if it is waiting to use the i 2 c bus). this is accomplished by enabling the i 2 c interrupt only during the aforementioned conditions. reading i2con rdat the data from sda is captured into areceive datao whenever a rising edge occurs on scl. rdat is also available (with seven low-order zeros) in the i2dat register. the difference between reading it here and there is that reading i2dat clears drdy, allowing the i 2 c to proceed on to another bit. typically, the first seven bits of a received byte are read from i2dat, while the 8th is read here. then i2dat can be written to send the acknowledge bit and clear drdy. atn aattentiono is 1 when one or more of drdy, arl, str, or stp is 1. thus, atn comprises a single bit that can be tested to release the i 2 c service routine from a await loop.o drdy adata readyo (and thus atn) is set when a rising edge occurs on scl, except at idle slave. drdy is cleared by writing cdr = 1, or by writing or reading the i2dat register. the following low period on scl is stretched until the program responds by clearing drdy.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 21 bit symbol function i2con.7 rdat read: the most recently received data bit. a cxa write: clears the transmit active flag. i2con.6 atn read: atn = 1 if any of the flags drdy, arl, str, or stp = 1. a idle write: in the i 2 c slave mode, writing a 1 to this bit causes the i 2 c hardware to ignore the bus until it is needed again. i2con.5 drdy read: data ready flag, set when there is a rising edge on scl. a cdr write: writing a 1 to this bit clears the drdy flag. i2con.4 arl read: arbitration loss flag, set when arbitration is lost while in the transmit mode. a carl write: writing a 1 to this bit clears the carl flag. i2con.3 str read: start flag, set when a start condition is detected at a master or non-idle slave. a cstr write: writing a 1 to this bit clears the str flag. i2con.2 stp read: stop flag, set when a stop condition is detected at a master or non-idle slave. a cstp write: writing a 1 to this bit clears the stp flag. i2con.1 master read: indicates whether this device is currently as bus master. a xstr write: writing a 1 to this bit causes a repeated start condition to be generated. i2con.0 e read: undefined. a xstp write: writing a 1 to this bit causes a stop condition to be generated. e su01155 master stp str arl drdy atn rdat 0 1 2 3 4 5 6 7 i2con reset value: 81h bit addressable 1 address: d8h xstp xstr cstp cstr carl cdr idle cxa read write figure 9. i 2 c control register (i2con) bit symbol function i2dat.7 rdat read: the most recently received data bit, captured from sda at every rising edge of scl. reading i2dat also clears drdy and the transmit active state. a xdat write: sets the data for the next transmitted bit. writing i2dat also clears drdy and sets the transmit active state. i2dat.60 unused. e su01156 e e e e e e rdat 0 1 2 3 4 5 6 7 i2dat reset value: xxh not bit addressable address: d9h e e e e e e e xdat read write figure 10. i 2 c data register (i2dat) checking atn and drdy when a program detects atn = 1, it should next check drdy. if drdy = 1, then if it receives the last bit, it should capture the data from rdat (in i2dat or i2con). next, if the next bit is to be sent, it should be written to i2dat. one way or another, it should clear drdy and then return to monitoring atn. note that if any of arl, str, or stp is set, clearing drdy will not release scl to high, so that the i 2 c will not go on to the next bit. if a program detects atn = 1, and drdy = 0, it should go on to examine arl, str, and stp.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 22 arl aarbitration losso is 1 when transmit active was set, but this device lost arbitration to another transmitter. transmit active is cleared when arl is 1. there are four separate cases in which arl is set. 1. if the program sent a 1 or repeated start, but another device sent a 0, or a stop, so that sda is 0 at the rising edge of scl. (if the other device sent a stop, the setting of arl will be followed shortly by stp being set.) 2. if the program sent a 1, but another device sent a repeated start, and it drove sda low before scl could be driven low. (this type of arl is always accompanied by str = 1.) 3. in master mode, if the program sent a repeated start, but another device sent a 1, and it drove scl low before this device could drive sda low. 4. in master mode, if the program sent stop, but it could not be sent because another device sent a 0. str astarto is set to a 1 when an i 2 c start condition is detected at a non-idle slave or at a master. (str is not set when an idle slave becomes active due to a start bit; the slave has nothing useful to do until the rising edge of scl sets drdy.) stp astopo is set to 1 when an i 2 c stop condition is detected at a non-idle slave or at a master. (stp is not set for a stop condition at an idle slave.) master amastero is 1 if this device is currently a master on the i 2 c. master is set when mastrq is 1 and the bus is not busy (i.e., if a start bit hasn't been received since reset or a atimer io time-out, or if a stop has been received since the last start). master is cleared when arl is set, or after the software writes mastrq = 0 and then xstp = 1. writing i2con typically, for each bit in an i 2 c message, a service routine waits for atn = 1. based on drdy, arl, str, and stp, and on the current bit position in the message, it may then write i2con with one or more of the following bits, or it may read or write the i2dat register. cxa writing a 1 to aclear xmit activeo clears the transmit active state. (reading the i2dat register also does this.) regarding transmit active transmit active is set by writing the i2dat register, or by writing i2con with xstr = 1 or xstp = 1. the i 2 c interface will only drive the sda line low when transmit active is set, and the arl bit will only be set to 1 when transmit active is set. transmit active is cleared by reading the i2dat register, or by writing i2con with cxa = 1. transmit active is automatically cleared when arl is 1. idle writing 1 to aidleo causes a slave's i 2 c hardware to ignore the i 2 c until the next start condition (but if mastrq is 1, then a stop condition will cause this device to become a master). cdr writing a 1 to aclear data readyo clears drdy. (reading or writing the i2dat register also does this.) carl wr iting a 1 to aclear arbitration losso clears the arl bit. cstr writing a 1 to aclear starto clears the str bit. cstp writing a 1 to aclear stopo clears the stp bit. note that if one or more of drdy, arl, str, or stp is 1, the low time of scl is stretched until the service routine responds by clearing them. xstr writing 1s to axmit repeated starto and cdr tells the i 2 c hardware to send a repeated start condition. this should only be at a master. note that xstr need not and should not be used to send an ainitialo (non-repeated) start; it is sent automatically by the i 2 c hardware. writing xstr = 1 includes the effect of writing i2dat with xdat = 1; it sets transmit active and releases sda to high during the scl low time. after scl goes high, the i 2 c hardware waits for the suitable minimum time and then drives sda low to make the start condition. xstp writing 1s to axmit stopo and cdr tells the i 2 c hardware to send a stop condition. this should only be done at a master. if there are no more messages to initiate, the service routine should clear the mastrq bit in i2cfg to 0 before writing xstp with 1. writing xstp = 1 includes the effect of writing i2dat with xdat = 0; it sets transmit active and drives sda low during the scl low time. after scl goes high, the i 2 c hardware waits for the suitable minimum time and then releases sda to high to make the stop condition.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 23 bit symbol function i2cfg.7 slaven slave enable. writing a 1 this bit enables the slave functions of the i 2 c subsystem. if slaven and mastrq are 0, the i 2 c hardware is disabled. this bit is cleared to 0 by reset and by an i 2 c time-out. i2cfg.6 mastrq master request. writing a 1 to this bit requests mastership of the i 2 c bus. if a transmission is in progress when this bit is changed from 0 to 1, action is delayed until a stop condition is detected. a start condition is sent and drdy is set (thus making atn = 1 and generating an i 2 c interrupt). when a master wishes to release mastership status of the i 2 c, it writes a 1 to xstp in i2con. mastrq is cleared by an i 2 c time-out. i2cfg.5 clrti writing a 1 to this bit clears the timer i overflow flag. this bit position always reads as a 0. i2cfg.4 tirun writing a 1 to this bit lets timer i run; a zero stops and clears it. together with slaven, mastrq, and master, this bit determines operational modes as shown in table 1. i2cfg.2, 3 e reserved for future use. should not be set to 1 by user programs. i2cfg.1, 0 ct1, ct0 these two bits are programmed as a function of the cpu clock rate, to optimize the min hi and lo time of scl when this device is a master on the i 2 c. the time value determined by these bits controls both of these parameters, and also the timing for stop and start conditions. ct0 su01157 ct1 e e tirun clrti mastrq slaven 0 1 2 3 4 5 6 7 i2cfg reset value: 00h bit addressable address: c8h figure 11. i 2 c configuration register (i2cfg) regarding software response time because the P87LPC768 can run at 20 mhz, and because the i 2 c interface is optimized for high-speed operation, it is quite likely that an i 2 c service routine will sometimes respond to drdy (which is set at a rising edge of scl) and write i2dat before scl has gone low again. if xdat were applied directly to sda, this situation would produce an i 2 c protocol violation. the programmer need not worry about this possibility because xdat is applied to sda only when scl is low. conversely, a program that includes an i 2 c service routine may take a long time to respond to drdy. typically, an i 2 c routine operates on a flag-polling basis during a message, with interrupts from other peripheral functions enabled. if an interrupt occurs, it will delay the response of the i 2 c service routine. the programmer need not worry about this very much either, because the i 2 c hardware stretches the scl low time until the service routine responds. the only constraint on the response is that it must not exceed the timer i time-out. values to be used in the ct1 and ct0 bits are shown in table 2. to allow the i 2 c bus to run at the maximum rate for a particular oscillator frequency, compare the actual oscillator rate to the f osc max column in the table. the value for ct1 and ct0 is found in the first line of the table where cpu clock max is greater than or equal to the actual frequency. table 2 also shows the machine cycle count for various settings of ct1/ct0. this allows calculation of the actual minimum high and low times for scl as follows: scl min high low time (in microseconds) 6 * min time count cpu clock (in mhz) for instance, at an 8 mhz frequency, with ct1/ct0 set to 1 0, the minimum scl high and low times will be 5.25 m s. table 2 also shows the timer i timeout period (given in machine cycles) for each ct1/ct0 combination. the timeout period varies because of the way in which minimum scl high and low times are measured. when the i 2 c interface is operating, timer i is pre-loaded at every scl transition with a value dependent upon ct1/ct0. the pre-load value is chosen such that a minimum scl high or low time has elapsed when timer i reaches a count of 008 (the actual value pre-loaded into timer i is 8 minus the machine cycle count).
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 24 table 2. interaction of tirun with slaven, mastrq, and master slaven, mastrq, master tirun operating mode all 0 0 the i 2 c interface is disabled. timer i is cleared and does not run. this is the state assumed after a reset. if an i 2 c application wants to ignore the i 2 c at certain times, it should write slaven, mastrq, and tirun all to zero. all 0 1 the i 2 c interface is disabled. any or all 1 0 the i 2 c interface is enabled. the 3 low-order bits of timer i run for min-time generation, but the hi-order bits do not, so that there is no checking for i 2 c being ahung.o this configuration can be used for very slow i 2 c operation. any or all 1 1 the i 2 c interface is enabled. timer i runs during frames on the i 2 c, and is cleared by transitions on scl, and by start and stop conditions. this is the normal state for i 2 c operation. table 3. ct1, ct0 values ct1, ct0 min time count (machine cycles) cpu clock max (for 100 khz i 2 c) timeout period (machine cycles) 1 0 7 8.4 mhz 1023 0 1 6 7.2 mhz 1022 0 0 5 6.0 mhz 1021 1 1 4 4.8 mhz 1020 interrupts the P87LPC768 uses a four priority level interrupt structure. this allows great flexibility in controlling the handling of the P87LPC768's many interrupt sources. the P87LPC768 supports up to 13 interrupt sources. each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers ien0 or ien1. the ien0 register also contains a global disable bit, ea, which disables all interrupts at once. each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the ip0, ip0h, ip1, and ip1h registers. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt source. so, if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level. table 3 summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake up the cpu from power down mode. table 4. summary of interrupts description interrupt flag bit(s) vector address interrupt enable bit(s) interrupt priority arbitration ranking power down wakeup external interrupt 0 ie0 0003h ex0 (ien0.0) ip0h.0, ip0.0 1 (highest) yes timer 0 interrupt tf0 000bh et0 (ien0.1) ip0h.1, ip0.1 4 no external interrupt 1 ie1 0013h ex1 (ien0.2) ip0h.2, ip0.2 7 yes timer 1 interrupt tf1 001bh et1 (ien0.3) ip0h.3, ip0.3 10 no serial port tx and rx ti & ri 0023h es (ien0.4) ip0h.4, ip0.4 12 no brownout detect bof 002bh ebo (ien0.5) ip0h.5, ip0.5 2 yes i 2 c interrupt atn 0033h ei2 (ien1.0) ip1h.0, ip1.0 5 no kbi interrupt kbf 003bh ekb (ien1.1) ip1h.1, ip1.1 8 yes comparator 2 interrupt cmf2 0043h ec2 (ien1.2) ip1h.2, ip1.2 11 yes watchdog timer wdovf 0053h ewd (ien0.6) ip0h.6, ip0.6 3 yes a/d converter adci 005bh ead (ien1.4) ip1h.4, ip1.4 6 yes comparator 1 interrupt cmf1 0063h ec1 (ien1.5) ip1h.5, ip1.5 9 yes timer 1 interrupt 0073h eti (ien 1.7) ip1h.7, ip1.7 13 (lowest) no
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 25 external interrupt inputs the P87LPC768 has two individual interrupt inputs as well as the keyboard interrupt function. the latter is described separately elsewhere in this section. the two interrupt inputs are identical to those present on the standard 80c51 microcontroller. the external sources can be programmed to be level-activated or transition-activated by setting or clearing bit it1 or it0 in register tcon. if itn = 0, external interrupt n is triggered by a detected low at the intn pin. if itn = 1, external interrupt n is edge triggered. in this mode if successive samples of the intn pin show a high in one cycle and a low in the next cycle, interrupt request flag ien in tcon is set, causing an interrupt request. since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 6 cpu clocks to ensure proper sampling. if the external interrupt is transition-activated, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle. this is to ensure that the transition is seen and that interrupt request flag ien is set. ien is automatically cleared by the cpu when the service routine is called. if the external interrupt is level-activated, the external source must hold the request active until the requested interrupt is actually generated. if the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated. it is not necessary to clear the interrupt flag ien when the interrupt is level sensitive, it simply tracks the input pin level. if an external interrupt is enabled when the P87LPC768 is put into power down or idle mode, the interrupt will cause the processor to wake up and resume operation. refer to the section on power reduction modes for details. su01401 wakeup (if in power down) ea (from ien0 register) interrupt to cpu ie0 ex0 ie1 ex1 bof ebo kbf ekb cm2 ec2 wdt ewd adc ead tf0 et0 tf1 et1 ri + ti es atn ei2 cm1 ec1 figure 12. interrupt sources, interrupt enables, and power down wakeup sources
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 26 i/o ports the P87LPC768 has 3 i/o ports, port 0, port 1, and port 2. the exact number of i/o pins available depend upon the oscillator and reset options chosen. at least 15 pins of the P87LPC768 may be used as i/os when a two-pin external oscillator and an external reset circuit are used. up to 18 pins may be available if fully on-chip oscillator and reset configurations are chosen. all but three i/o port pins on the P87LPC768 may be software configured to one of four types on a bit-by-bit basis, as shown in table 4. these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and input only. two configuration registers for each port choose the output type for each port pin. table 5. port output configuration settings pxm1.y pxm2.y port output mode 0 0 quasi-bidirectional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain quasi-bidirectional output configuration the default port output configuration for standard P87LPC768 i/o ports is the quasi-bidirectional output that is common on the 80c51 and most of its derivatives. this output type can be used as both an input and output without the need to reconfigure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is pulled low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. one of these pull-ups, called the avery weako pull-up, is turned on whenever the port latch for the pin contains a logic 1. the very weak pull-up sources a very small current that will pull the pin high if it is left floating. a second pull-up, called the aweako pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. if a pin that has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and take the voltage on the port pin below its input threshold. the third pull-up is referred to as the astrongo pull-up. this pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. when this occurs, the strong pull-up turns on for a brief time, two cpu clocks, in order to pull the port pin high quickly. then it turns off again. the quasi-bidirectional port configuration is shown in figure 13. su01159 weak very weak strong port pin v dd 2 cpu clock delay input data port latch data n ppp figure 13. quasi-bidirectional output
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 27 open drain output configuration the open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. to be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to v dd . the pull-down for this mode is the same as for the quasi-bidirectional mode. the open drain port configuration is shown in figure 14. push-pull output configuration the push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. the push-pull port configuration is shown in figure 15. the three port pins that cannot be configured are p1.2, p1.3, and p1.5. the port pins p1.2 and p1.3 are permanently configured as open drain outputs. they may be used as inputs by writing ones to their respective port latches. p1.5 may be used as a schmitt trigger input if the P87LPC768 has been configured for an internal reset and is not using the external reset input function rst. additionally, port pins p2.0 and p2.1 are disabled for both input and output if one of the crystal oscillator options is chosen. those options are described in the oscillator section. the value of port pins at reset is determined by the prhi bit in the ucfg1 register. ports may be configured to reset high or low as needed for the application. when port pins are driven high at reset, they are in quasi-bidirectional mode and therefore do not source large amounts of current. every output on the P87LPC768 may potentially be used as a 20 ma sink led drive output. however, there is a maximum total output current for all ports which must not be exceeded. all ports pins of the P87LPC768 have slew rate controlled outputs. this is to limit noise generated by quickly switching output signals. the slew rate is factory set to approximately 10 ns rise and fall times. the bits in the p2m1 register that are not used to control configuration of p2.1 and p2.0 are used for other purposes. these bits can enable schmitt trigger inputs on each i/o port, enable toggle outputs from timer 0 and timer 1, and enable a clock output if either the internal rc oscillator or external clock input is being used. the last two functions are described in the timer/counters and oscillator sections respectively. the enable bits for all of these functions are shown in figure 16. each i/o port of the P87LPC768 may be selected to use ttl level inputs or schmitt inputs with hysteresis. a single configuration bit determines this selection for the entire port. port pins p1.2, p1.3, and p1.5 always have a schmitt trigger input. su01160 port pin input data port latch data n figure 14. open drain output su01161 port pin v dd input data port latch data n p figure 15. push-pull output
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 28 bit symbol function p2m1.7 p2s when p2s = 1, this bit enables schmitt trigger inputs on port 2. p2m1.6 p1s when p1s = 1, this bit enables schmitt trigger inputs on port 1. p2m1.5 p0s when p0s = 1, this bit enables schmitt trigger inputs on port 0. p2m1.4 enclk when enclk is set and the P87LPC768 is configured to use the on-chip rc oscillator, a clock output is enabled on the x2 pin (p2.0). refer to the oscillator section for details. p2m1.3 ent1 when set, the p.7 pin is toggled whenever timer 1 overflows. the output frequency is therefore one half of the timer 1 overflow rate. refer to the timer/counters section for details. p2m1.2 ent0 when set, the p1.2 pin is toggled whenever timer 0 overflows. the output frequency is therefore one half of the timer 0 overflow rate. refer to the timer/counterssection for details. p2m1.1, p2m1.0 e these bits, along with the matching bits in the p2m2 register, control the output configuration of p2.1 and p2.0 respectively, as shown in table 4. (p2m1.0) su01636 (p2m1.1) ent0 ent1 enclk p0s p1s p2s 0 1 2 3 4 5 6 7 p2m1 reset value: 00h not bit addressable address: a4h figure 16. port 2 mode register 1 (p2m1) keyboard interrupt (kbi) the keyboard interrupt function is intended primarily to allow a single interrupt to be generated when any key is pressed on a keyboard or keypad connected to specific pins of the P87LPC768, as shown in figure 17. this interrupt may be used to wake up the cpu from idle or power down modes. this feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption yet also need to be convenient to use. the P87LPC768 allows any or all pins of port 0 to be enabled to cause this interrupt. port pins are enabled by the setting of bits in the kbi register, as shown in figure 18. the keyboard interrupt flag (kbf) in the auxr1 register is set when any enabled pin is pulled low while the kbi interrupt function is active. an interrupt will generated if it has been enabled. note that the kbf bit must be cleared by software. due to human time scales and the mechanical delay associated with keyswitch closures, the kbi feature will typically allow the interrupt service routine to poll port 0 in order to determine which key was pressed, even if the processor has to wake up from power down mode. refer to the section on power reduction modes for details.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 29 su01163 kbf (kbi interrupt) ekb (from ien1 register) p0.7 kbi.7 p0.6 kbi.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 kbi.5 kbi.4 kbi.3 kbi.2 kbi.1 kbi.0 figure 17. keyboard interrupt bit symbol function kbi.7 kbi.7 when set, enables p0.7 as a cause of a keyboard interrupt. kbi.6 kbi.6 when set, enables p0.6 as a cause of a keyboard interrupt. kbi.5 kbi.5 when set, enables p0.5 as a cause of a keyboard interrupt. kbi.4 kbi.4 when set, enables p0.4 as a cause of a keyboard interrupt. kbi.3 kbi.3 when set, enables p0.3 as a cause of a keyboard interrupt. kbi.2 kbi.2 when set, enables p0.2 as a cause of a keyboard interrupt. kbi.1 kbi.1 when set, enables p0.1 as a cause of a keyboard interrupt. kbi.0 kbi.0 when set, enables p0.0 as a cause of a keyboard interrupt. note: the keyboard interrupt must be enabled in order for the settings of the kbi register to be effective. the interrupt flag (kbf) is located at bit 7 of auxr1. kbi.0 su01164 kbi.1 kbi.2 kbi.3 kbi.4 kbi.5 kbi.6 kbi.7 0 1 2 3 4 5 6 7 kbi reset value: 00h not bit addressable address: 86h figure 18. keyboard interrupt register (kbi)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 30 oscillator the P87LPC768 provides several user selectable oscillator options, allowing optimization for a range of needs from high precision to lowest possible cost. these are configured when the eprom is programmed. basic oscillator types that are supported include: low, medium, and high speed crystals, covering a range from 20 khz to 20 mhz; ceramic resonators; and on-chip rc oscillator. low frequency oscillator option this option supports an external crystal in the range of 20 khz to 100 khz. table 6 shows capacitor values that may be used with a quartz crystal in this mode. table 6. recommended oscillator capacitors for use with the low frequency oscillator option oscillator v dd = 2.7 to 4.5 v v dd = 4.5 to 6.0 v frequency lower limit optimal value upper limit lower limit optimal value upper limit 20 khz 15 pf 15 pf 33 pf 33 pf 33 pf 47 pf 32 khz 15 pf 15 pf 33 pf 33 pf 33 pf 47 pf 100 khz 15 pf 15 pf 33 pf 15 pf 15 pf 33 pf medium frequency oscillator option this option supports an external crystal in the range of 100 khz to 4 mhz. ceramic resonators are also supported in this config uration. table 7 shows capacitor values that may be used with a quartz crystal in this mode. table 7. recommended oscillator capacitors for use with the medium frequency oscillator option oscillator freq ency v dd = 2.7 to 4.5 v oscillator freq u ency lower limit optimal value upper limit 100 khz 33 pf 33 pf 47 pf 1 mhz 15 pf 15 pf 33 pf 4 mhz 15 pf 15 pf 33 pf high frequency oscillator option this option supports an external crystal in the range of 4 to 20 mhz. ceramic resonators are also supported in this configurati on. table 8 shows capacitor values that may be used with a quartz crystal in this mode. table 8. recommended oscillator capacitors for use with the high frequency oscillator option oscillator v dd = 2.7 to 4.5 v v dd = 4.5 to 6.0 v frequency lower limit optimal value upper limit lower limit optimal value upper limit 4 mhz 15 pf 33 pf 47 pf 15 pf 33 pf 68 pf 8 mhz 15 pf 15 pf 33 pf 15 pf 33 pf 47 pf 16 mhz 15 pf 15 pf 33 pf 20 mhz 15 pf 15 pf 33 pf on-chip rc oscillator option the on-chip rc oscillator option has a typical frequency of 6 mhz and can be divided down for slower operation through the use of the divm register. note that the on-chip oscillator has a 25% frequency tolerance and for that reason may not be suitable for use in some applications. a clock output on the x2/p2.0 pin may be enabled when the on-chip rc oscillator is used. external clock input option in this configuration, the processor clock is input from an external source driving the x1/p2.1 pin. the rate may be from 0 hz up to 20 mhz when v dd is above 4.5 v and up to 10 mhz when v dd is below 4.5 v. when the external clock input mode is used, the x2/p2.0 pin may be used as a standard port pin. a clock output on the x2/p2.0 pin may be enabled when the external clock input is used. clock output the P87LPC768 supports a clock output function when either the on-chip rc oscillator or external clock input options are selected. this allows external devices to synchronize to the P87LPC768. when enabled, via the enclk bit in the p2m1 register, the clock output appears on the x2/clkout pin whenever the on-chip oscillator is running, including in idle mode. the frequency of the clock output is 1/6 of the cpu clock rate. if the clock output is not needed in idle mode, it may be turned off prior to entering idle, saving additional power. the clock output may also be enabled when the external clock input option is selected.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 31 su01389 87lpc768 quartz crystal or ceramic resonator x2 x1 the oscillator must be configured in one of the following modes: low frequency crystal medium frequency crystal high frequency crystal * capacitor values may be optimized for different oscillator frequencies (see text) a series resistor may be required in order to limit crystal drive levels. this is particularly important for low frequency crystals (see text). figure 19. using the crystal oscillator su01390 87lpc768 x2 x1 the oscillator must be configured in the external clock input mode. a clock output may be obtained on the x2 pin by setting the enclk bit in the p2m1 register. cmos compatible external oscillator signal figure 20. using an external clock input
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 32 su01167 clock select clock sources clock out xtal select internal rc oscillator crystal: low frequency crystal: medium frequency crystal: high frequency external clock input 10-bit ripple counter reset count count 256 count 1024 oscillator startup timer divide-by-m (divm register) and clkr select cpu clock 1/ 2 clkr (ucfg1.3) power down power monitor reset fosc0 (ucfg1.0) fosc1 (ucfg1.1) fosc2 (ucfg1.2) figure 21. block diagram of oscillator control cpu clock modification: clkr and divm for backward compatibility, the clkr configuration bit allows setting the P87LPC768 instruction and peripheral timing to match standard 80c51 timing by dividing the cpu clock by two. default timing for the P87LPC768 is 6 cpu clocks per machine cycle while standard 80c51 timing is 12 clocks per machine cycle. this division also applies to peripheral timing, allowing 80c51 code that is oscillator frequency and/or timer rate dependent. the clkr bit is located in the eprom configuration register ucfg1, described under eprom characteristics in addition to this, the cpu clock may be divided down from the oscillator rate by a programmable divider, under program control. this function is controlled by the divm register. if the divm register is set to zero (the default value), the cpu will be clocked by either the unmodified oscillator rate, or that rate divided by two, as determined by the previously described clkr function. when the divm register is set to some value n (between 1 and 255), the cpu clock is divided by 2 * (n + 1). clock division values from 4 through 512 are thus possible. this feature makes it possible to temporarily run the cpu at a lower rate, reducing power consumption, in a manner similar to idle mode. by dividing the clock, the cpu can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the idle mode) by executing its normal program at a lower rate. this can allow bypassing the oscillator startup time in cases where power down mode would otherwise be used. the value of divm may be changed by the program at any time without interrupting code execution. power monitoring functions the P87LPC768 incorporates power monitoring functions designed to prevent incorrect operation during initial power up and power loss or reduction during operation. this is accomplished with two hardware functions: power-on detect and brownout detect. brownout detection the brownout detect function allows preventing the processor from failing in an unpredictable manner if the power supply voltage drops below a certain level. the default operation is for a brownout detection to cause a processor reset, however it may alternatively be configured to generate an interrupt by setting the boi bit in the auxr1 register (auxr1.5). the P87LPC768 allows selection of two brownout levels: 2.5 v or 3.8 v. when v dd drops below the selected voltage, the brownout detector triggers and remains active until v dd is returns to a level above the brownout detect voltage. when brownout detect causes a processor reset, that reset remains active as long as v dd remains below the brownout detect voltage. when brownout detect generates an interrupt, that interrupt occurs once as v dd crosses from above to below the brownout detect voltage. for the interrupt to be processed, the interrupt system and the boi interrupt must both be enabled (via the ea and ebo bits in ien0). when brownout detect is activated, the bof flag in the pcon register is set so that the cause of processor reset may be determined by software. this flag will remain set until cleared by software.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 33 for correct activation of brownout detect, the v dd fall time must be no faster than 50 mv/ m s. when v dd is restored, is should not rise faster than 2 mv/ m s in order to insure a proper reset. the brownout voltage (2.5 v or 3.8 v) is selected via the bov bit in the eprom configuration register ucfg1. when unprogrammed (bov = 1), the brownout detect voltage is 2.5 v. when programmed (bov = 0), the brownout detect voltage is 3.8 v. if the brownout detect function is not required in an application, it may be disabled, thus saving power. brownout detect is disabled by setting the control bit bod in the auxr1 register (auxr1.6). power on detection the power on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. when this feature is activated, the pof flag in the pcon register is set to indicate an initial power up condition. the pof flag will remain set until cleared by software. power reduction modes the P87LPC768 supports idle and power down modes of power reduction. idle mode the idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. any enabled interrupt source or reset may terminate idle mode. idle mode is entered by setting the idl bit in the pcon register (see figure 22). power down mode the power down mode stops the oscillator in order to absolutely minimize power consumption. power down mode is entered by setting the pd bit in the pcon register (see figure 22). the processor can be made to exit power down mode via reset or one of the interrupt sources shown in table 5. this will occur if the interrupt is enabled and its priority is higher than any interrupt currently in progress. in power down mode, the power supply voltage may be reduced to the ram keep-alive voltage v ram . this retains the ram contents at the point where power down mode was entered. sfr contents are not guaranteed after v dd has been lowered to v ram , therefore it is recommended to wake up the processor via reset in this case. v dd must be raised to within the operating range before the power down mode is exited. since the watchdog timer has a separate oscillator, it may reset the processor upon overflow if it is running during power down. note that if the brownout detect reset is enabled, the processor will be put into reset as soon as v dd drops below the brownout voltage. if brownout detect is configured as an interrupt and is enabled, it will wake up the processor from power down mode when v dd drops below the brownout voltage. when the processor wakes up from power down mode, it will start the oscillator immediately and begin execution when the oscillator is stable. oscillator stability is determined by counting 1024 cpu clocks after start-up when one of the crystal oscillator configurations is used, or 256 clocks after start-up for the internal rc or external clock input configurations. some chip functions continue to operate and draw power during power down mode, increasing the total power used during power down. these include the brownout detect, watchdog timer, comparators, and a/d converter. bit symbol function pcon.7 smod1 when set, this bit doubles the uart baud rate for modes 1, 2, and 3. pcon.6 smod0 this bit selects the function of bit 7 of the scon sfr. when 0, scon.7 is the sm0 bit. when 1, scon.7 is the fe (framing error) flag. see figure 26 for additional information. pcon.5 bof brown out flag. set automatically when a brownout reset or interrupt has occurred. also set at power on. cleared by software. refer to the power monitoring functions section for additional information. pcon.4 pof power on flag. set automatically when a power-on reset has occurred. cleared by software. refer to the power monitoring functions section for additional information. pcon.3 gf1 general purpose flag 1. may be read or written by user software, but has no effect on operation. pcon.2 gf0 general purpose flag 0. may be read or written by user software, but has no effect on operation. pcon.1 pd power down control bit. setting this bit activates power down mode operation. cleared when the power down mode is terminated (see text). pcon.0 idl idle mode control bit. setting this bit activates idle mode operation. cleared when the idle mode is terminated (see text). idl su01168 pd gf0 gf1 pof bof smod0 smod1 0 1 2 3 4 5 6 7 pcon reset value: 30h for a power on reset 20h for a brownout reset 00h for other reset sources not bit addressable address: 87h figure 22. power control register (pcon)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 34 table 9. sources of wakeup from power down mode wakeup source conditions external interrupt 0 or 1 the corresponding interrupt must be enabled. keyboard interrupt the keyboard interrupt feature must be enabled and properly set up. the corresponding interrupt must be enabled. comparator 1 or 2 the comparator(s) must be enabled and properly set up. the corresponding interrupt must be enabled. watchdog timer reset the watchdog timer must be enabled via the wdte bit in the ucfg1 eprom configuration byte. watchdog timer interrupt the wdte bit in the ucfg1 eprom configuration byte must not be set. the corresponding interrupt must be enabled. brownout detect reset the bod bit in auxr1 must not be set (brownout detect not disabled). the boi bit in auxr1 must not be set (brownout interrupt disabled). brownout detect interrupt the bod bit in auxr1 must not be set (brownout detect not disabled). the boi bit in auxr1 must be set (brownout interrupt enabled). the corresponding interrupt must be enabled. reset input the external reset input must be enabled. a/d converter must use internal rc clock (rcclk = 1) for a/d converter to work in power down mode. the a/d must be enabled and properly set up. the corresponding interrupt must be enabled.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 35 low voltage eprom operation the eprom array contains some analog circuits that are not required when v dd is less than 4 v, but are required for a v dd greater than 4 v. the lpep bit (auxr.4), when set by software, will power down these analog circuits resulting in a reduced supply current. lpep is cleared only by power-on reset, so it may be set only for applications that always operate with v dd less than 4 v. reset the P87LPC768 has an integrated power-on reset circuit which always provides a reset when power is initially applied to the device. it is recommended to use the internal reset whenever possible to save external components and to be able to use pin p1.5 as a general-purpose input pin. the P87LPC768 can additionally be configured to use p1.5 as an external active-low reset pin rst by programming the rpd bit in the user configuration register ucfg1 to 0. the internal reset is still active on power-up of the device. while the signal on the rst pin is low, the P87LPC768 is held in reset until the signal goes high. the watchdog timer on the P87LPC768 can act as an oscillator fail detect because it uses an independent, fully on-chip oscillator. ucfg1 is described in the system configuration bytes section of this datasheet. su01391 87lpc768 p1.5 pin is used as digital input pin internal power-on reset active ucfg1.rpd = 1 (default) 87lpc768 rst pin is used as active-low reset pin internal power-on reset active ucfg1.rpd = 0 figure 23. using pin p1.5 as general purpose input pin or as low-active reset pin su01170 chip reset cpu clock q reset timing rpd (ucfg1.6) wdt module software reset srst (auxr1.3) power monitor reset rst /v pp pin wdte (ucfg1.7) s r figure 24. block diagram showing reset sources
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 36 timer/counters the P87LPC768 has two general purpose counter/timers which are upward compatible with the standard 80c51 timer 0 and timer 1. both can be configured to operate either as timers or event counters (see figure 25). an option to automatically toggle the t0 and/or t1 pins upon timer overflow has been added. in the atimero function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of 6 cpu clock periods, the count rate is 1/6 of the cpu clock frequency. refer to the section enhanced cpu for a description of the cpu clock. in the acountero function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled once during every machine cycle. when the samples of the pin state show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during the cycle following the one in which the transition was detected. since it takes 2 machine cycles (12 cpu clocks) to recognize a 1-to-0 transition, the maximum count rate is 1/6 of the cpu clock frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. the atimero or acountero function is selected by control bits c/t in the special function register tmod. in addition to the atimero or acountero selection, timer 0 and timer 1 have four operating modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. bit symbol function tmod.7 gate gating control for timer 1. when set, timer/counter is enabled only while the int1 pin is high and the tr1 control pin is set. when cleared, timer 1 is enabled when the tr1 control bit is set. tmod.6 c/t timer or counter selector for timer 1. cleared for timer operation (input from internal system clock.) set for counter operation (input from t1 input pin). tmod.5, 4 m1, m0 mode select for timer 1 (see table below). tmod.3 gate gating control for timer 0. when set, timer/counter is enabled only while the int0 pin is high and the tr0 control pin is set. when cleared, timer 0 is enabled when the tr0 control bit is set. tmod.2 c/t timer or counter selector for timer 0. cleared for timer operation (input from internal system clock.) set for counter operation (input from t0 input pin). tmod.1, 0 m1, m0 mode select for timer 0 (see table below). m1, m0 timer mode 0 0 8048 timer atlno serves as 5-bit prescaler. 0 1 16-bit timer/counter athno and atlno are cascaded; there is no prescaler. 1 0 8-bit auto-reload timer/counter. thn holds a value which is loaded into tln when it overflows. 1 1 timer 0 is a dual 8-bit timer/counter in this mode. tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only, controlled by the timer 1 control bits (see text). timer 1 in this mode is stopped. m0 su01171 m1 c/t gate m0 m1 c/t gate 0 1 2 3 4 5 6 7 tmod reset value: 00h not bit addressable address: 89h t1 t0 figure 25. timer/counter mode control register (tmod)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 37 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 27 shows mode 0 operation. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfn. the count input is enabled to the timer when trn = 1 and either gate = 0 or intn = 1. (setting gate = 1 allows the timer to be controlled by external input intn , to facilitate pulse width measurements). trn is a control bit in the special function register tcon (figure 26). the gate bit is in the tmod register. the 13-bit register consists of all 8 bits of thn and the lower 5 bits of tln. the upper 3 bits of tln are indeterminate and should be ignored. setting the run flag (trn) does not clear the registers. mode 0 operation is the same for timer 0 and timer 1. see figure 27. there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). bit symbol function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when the interrupt is processed, or by software. tcon.6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter 1 on/off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when the processor vectors to the interrupt routine, or by software. tcon.4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter 0 on/off. tcon.3 ie1 interrupt 1 edge flag. set by hardware when external interrupt 1 edge is detected. cleared by hardware when the interrupt is processed, or by software. tcon.2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. tcon.1 ie0 interrupt 0 edge flag. set by hardware when external interrupt 0 edge is detected. cleared by hardware when the interrupt is processed, or by software. tcon.0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. it0 su01172 ie0 it1 ie1 tr0 tf0 tr1 tf1 0 1 2 3 4 5 6 7 tcon reset value: 00h bit addressable address: 88h figure 26. timer/counter control register (tcon) su01173 tln (5 bits) thn (8 bits) osc/6 or osc/12 overflow tn pin tnoe toggle control c/t = 1 c/t = 0 tn pin trn gate intn pin interrupt tfn figure 27. timer/counter 0 or 1 in mode 0 (13-bit counter)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 38 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register (thn and tln) are used. see figure 28 mode 2 mode 2 configures the timer register as an 8-bit counter (tl1) with automatic reload, as shown in figure 29. overflow from tln not only sets tfn, but also reloads tln with the contents of thn, which must be preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer 0 and timer 1. mode 3 when timer 1 is in mode 3 it is stopped. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate 8-bit counters. the logic for mode 3 on timer 0 is shown in figure 30. tl0 uses the timer 0 control bits: c/t, gate, tr0, int0 , and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the atimer 1o interrupt. mode 3 is provided for applications that require an extra 8-bit timer. with timer 0 in mode 3, an P87LPC768 can look like it has three timer/counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it into and out of its own mode 3. it can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt. su01174 tln (8 bits) thn (8 bits) osc/6 or osc/12 overflow tn pin tnoe toggle control c/t = 1 c/t = 0 tn pin trn gate intn pin interrupt tfn figure 28. timer/counter 0 or 1 in mode 1 (16-bit counter) su01175 tln (8-bits) thn (8-bits) osc/6 or osc/12 overflow tn pin tnoe toggle control c/t = 1 c/t = 0 tn pin trn gate intn pin interrupt tfn reload figure 29. timer/counter 0 or 1 in mode 2 (8-bit auto-reload)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 39 su01176 tl0 (8 bits) osc/6 or osc/12 overflow t0 pin t0oe toggle control c/t = 1 c/t = 0 t0 pin tr0 gate int0 pin interrupt tf0 th0 (8 bits) overflow t1 pin t1oe toggle control interrupt tf1 tr1 osc/6 or osc/12 figure 30. timer/counter 0 mode 3 (two 8-bit counters) timer overflow toggle output timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. the same device pins that are used for the t0 and t1 count inputs are also used for the timer toggle outputs. this function is enabled by control bits t0oe and t1oe in the p2m1 register, and apply to timer 0 and timer 1 respectively. the port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. uart the P87LPC768 includes an enhanced 80c51 uart. the baud rate source for the uart is timer 1 for modes 1 and 3, while the rate is fixed in modes 0 and 2. because cpu clocking is different on the P87LPC768 than on the standard 80c51, baud rate calculation is somewhat different. enhancements over the standard 80c51 uart include framing error detection and automatic address recognition. the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the sbuf register. however, if the first byte still hasn't been read by the time reception of the second byte is complete, the first byte will be lost. the serial port receive and transmit registers are both accessed through special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can be operated in 4 modes: mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted or received, lsb first. the baud rate is fixed at 1/6 of the cpu clock frequency. mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb first), and a stop bit (logical 1). when data is received, the stop bit is stored in rb8 in special function register scon. the baud rate is variable and is determined by the timer 1 overflow rate. mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logical 0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (logical 1). when data is transmitted, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. when data is received, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/16 or 1/32 of the cpu clock frequency, as determined by the smod1 bit in pcon. mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (logical 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 overflow rate. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 40 serial port control register (scon) the serial port control and status register is the special function register scon, shown in figure 31. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). the framing error bit (fe) allows detection of missing stop bits in the received data stream. the fe bit shares the bit position scon.7 with the sm0 bit. which bit appears in scon at any particular time is determined by the smod0 bit in the pcon register. if smod0 = 0, scon.7 is the sm0 bit. if smod0 = 1, scon.7 is the fe bit. once set, the fe bit remains set until it is cleared by software. this allows detection of framing errors for a group of characters without the need for monitoring it for every character individually. bit symbol function scon.7 fe framing error. this bit is set by the uart receiver when an invalid stop bit is detected. must be cleared by software. the smod0 bit in the pcon register must be 1 for this bit to be accessible. see sm0 bit below. scon.7 sm0 with sm1, defines the serial port mode. the smod0 bit in the pcon register must be 0 for this bit to be accessible. see fe bit above. scon. 6 sm1 with sm0, defines the serial port mode (see table below). sm0, sm1 uart mode baud rate 0 0 0: shift register cpu clock/6 0 1 1: 8-bit uart variable (see text) 1 0 2: 9-bit uart cpu clock/32 or cpu clock/16 1 1 3: 9-bit uart variable (see text) scon.5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then rl will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. scon.4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. scon.3 tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. scon.2 rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2=0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. scon.1 ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. scon.0 ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. ri su01157 ti rb8 tb8 ren sm2 sm1 sm0/fe 0 1 2 3 4 5 6 7 scon reset value: 00h bit addressable address: 98h figure 31. serial port control register (scon)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 41 baud rates the baud rate in mode 0 is fixed: mode 0 baud rate = cpu clock/6. the baud rate in mode 2 depends on the value of bit smod1 in special function register pcon. if smod1 = 0 (which is the value on reset), the baud rate is 1/32 of the cpu clock frequency. if smod1 = 1, the baud rate is 1/16 of the cpu clock frequency. mode 2 baud rate 1 smod1 32 cpu clock frequency using timer 1 to generate baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod1. the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either atimero or acountero operation, and in any of its 3 running modes. in the most typical applications, it is configured for atimero operation, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1, 3 baud rate cpu clock frequency 192(or96ifsmod1 1) 256 (th1) tables 6 and 7 list various commonly used baud rates and how they can be obtained using timer 1 as the baud rate generator. table 10. baud rates, timer values, and cpu clock frequencies for smod1 = 0 timer co nt baud rate timer co u nt 2400 4800 9600 19.2k 38.4k 57.6k 1 0.4608 0.9216 * 1.8432 * 3.6864 * 7.3728 * 11.0592 2 0.9216 1.8432 * 3.6864 * 7.3728 * 14.7456 3 1.3824 2.7648 5.5296 * 11.0592 4 * 1.8432 * 3.6864 * 7.3728 * 14.7456 5 2.3040 4.6080 9.2160 * 18.4320 6 2.7648 5.5296 * 11.0592 7 3.2256 6.4512 12.9024 8 * 3.6864 * 7.3728 * 14.7456 9 4.1472 8.2944 16.5888 10 4.6080 9.2160 * 18.4320
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 42 table 11. baud rates, timer values, and cpu clock frequencies for smod1 = 1 timer co nt baud rate timer co u nt 2400 4800 9600 19.2k 38.4k 57.6k 115.2k 1 0.2304 0.4608 0.9216 * 1.8432 * 3.6864 5.5296 * 11.0592 2 0.4608 0.9216 * 1.8432 * 3.6864 * 7.3728 * 11.0592 3 0.6912 1.3824 2.7648 5.5296 * 11.0592 16.5888 4 0.9216 * 1.8432 * 3.6864 * 7.3728 * 14.7456 5 1.1520 2.3040 4.6080 9.2160 * 18.4320 6 1.3824 2.7648 5.5296 * 11.0592 7 1.6128 3.2256 6.4512 12.9024 8 * 1.8432 * 3.6864 * 7.3728 * 14.7456 9 2.0736 4.1472 8.2944 16.5888 10 2.3040 4.6080 9.2160 * 18.4320 11 2.5344 5.0688 10.1376 12 2.7648 5.5296 * 11.0592 13 2.9952 5.9904 11.9808 14 3.2256 6.4512 12.9024 15 3.4560 6.9120 13.8240 16 * 3.6864 * 7.3728 * 14.7456 17 3.9168 7.8336 15.6672 18 4.1472 8.2944 16.5888 19 4.3776 8.7552 17.5104 20 4.6080 9.2160 * 18.4320 21 4.8384 9.6768 19.3536 notes to tables 10 and 11: 1. tables 6 and 7 apply to uart modes 1 and 3 (variable rate modes), and show cpu clock rates in mhz for standard baud rates fro m 2400 to 115.2k baud. 2. table 6 shows timer settings and cpu clock rates with the smod1 bit in the pcon register = 0 (the default after reset), while table 7 reflects the smod1 bit = 1. 3. the tables show all potential cpu clock frequencies up to 20 mhz that may be used for baud rates from 9600 baud to 115.2k bau d. other cpu clock frequencies that would give only lower baud rates are not shown. 4. table entries marked with an asterisk (*) indicate standard crystal and ceramic resonator frequencies that may be obtained fr om many sources without special ordering.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 43 more about uart mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb first). the baud rate is fixed at 1/6 the cpu clock frequency. figure 32 shows a simplified functional diagram of the serial port in mode 0, and associated timing. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal at s6p2 also loads a 1 into the 9th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between awrite to sbufo and activation of send. send enables the output of the shift register to the alternate output function line of p1.1 and also enable shift clock to the alternate output function line of p1.0. shift clock is low during s3, s4, and s5 of every machine cycle, and high during s6, s1, and s2. at s6p2 of every machine cycle in which send is active, the contents of the transmit shift are shifted to the right one position. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control block to do one last shift and then deactivate send and set t1. both of these actions occur at s1p1 of the 10th machine cycle after awrite to sbuf.o reception is initiated by the condition ren = 1 and r1 = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 1 1111110 t o the receive shift register, and in the next clock phase activates receive. receive enable shift clock to the alternate output function line of p1.0. shift clock makes transitions at s3p1 and s6p1 of every machine cycle. at s6p2 of every machine cycle in which receive is active, the contents of the receive shift register are shifted to the left one position. the value that comes in from the right is the value that was sampled at the p1.1 pin at s5p2 of the same machine cycle. as data bits come in from the right, 1s shift out to the left. when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle after the write to scon that cleared ri, receive is cleared as ri is set. more about uart mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the P87LPC768 the baud rate is determined by the timer 1 overflow rate. figure 33 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit receive. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads a 1 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 10th divide-by-16 rollover after awrite to sbuf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. r1 = 0, and 2. either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. at this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in rxd.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 44 80c51 internal bus su01178 80c51 internal bus write to sbuf sbuf zero detector rxd p1.1 alt output function tx control s tx clock start q cl d serial port interrupt shift clock shift send s6 rxd p1.1 alt input function load sbuf ti input shift register start ri receive shift tx clock rx control ren ri sbuf read sbuf transmit txd p1.0 alt output function send rxd (data out) d0 d1 d5 d2 d6 d3 d4 d7 txd (shift clock) shift s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 s1 ... s6 write to sbuf ti receive receive d0 d1 d5 d2 d6 d3 d4 d7 txd (shift clock) shift write to scon (clear ri) ri rxd (data in) 11 111 11 0 figure 32. serial port mode 0
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 45 su01179 80c51 internal bus write to sbuf sbuf zero detector txd p1.0 alt output function tx control s tx clock start q cl d serial port interrupt shift send load sbuf ti input shift register start ri load sbuf shift rx clock 1ffh rx control sbuf read sbuf transmit rxd p1.1 alt input function 80c51 internal bus data tb8 16 16 2 timer 1 overflow smod1 = 0 smod1 = 1 1-to-0 transition detector bit detector start bit stop bit tx clock write to sbuf send data shift txd ti d0 d1 d5 d2 d6 d3 d4 d7 receive rx clock shift ri bit detector sample times start bit stop bit rxd d0 d1 d5 d2 d6 d3 d4 d7 16 reset figure 33. serial port mode 1
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 46 more about uart modes 2 and 3 eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8) can be assigned the value of 0 or 1. on receive, the 9the data bit goes into rb8 in scon. the baud rate is programmable to either 1/16 or 1/32 of the cpu clock frequency in mode 2. mode 3 may have a variable baud rate generated from timer 1. figures 34 and 35 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads tb8 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. thereafter, only zeros are clocked in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 11th divide-by-16 rollover after awrite to sbuf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rd. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. ri = 0, and 2. either sm2 = 0, or the received 9th data bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the first 8 data bits go into sbuf. one bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the rxd input. multiprocessor communications uart modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received or transmitted. when data is received, the 9th bit is stored in rb8. the uart can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. one way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that follow. the slaves that weren't being addressed leave their sm2 bits set and go on about their business, ignoring the subsequent data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit, although this is better done with the framing error flag. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 47 start bit su01180 80c51 internal bus write to sbuf sbuf zero detector txd p1.0 alt output function tx control s tx clock start q cl d serial port interrupt shift send load sbuf ti input shift register start ri load sbuf shift rx clock 1ffh rx control sbuf read sbuf rxd p1.1 alt input function 80c51 internal bus data tb8 16 16 2 phase 2 clock (1/2 f osc ) 1-to-0 transition detector bit detector stop bit gen. smod1 = 0 smod1 = 1 transmit start bit stop bit tx clock write to sbuf send data shift txd ti d0 d1 d5 d2 d6 d3 d4 d7 receive rx clock shift ri bit detector sample times stop bit rxd d0 d1 d5 d2 d6 d3 d4 d7 16 reset tb8 stop bit gen. rb8 figure 34. serial port mode 2
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 48 bit detector su01181 transmit start bit stop bit tx clock write to sbuf send data shift txd ti d0 d1 d5 d2 d6 d3 d4 d7 receive rx clock shift ri bit detector sample times start bit stop bit rxd d0 d1 d5 d2 d6 d3 d4 d7 16 reset tb8 stop bit gen. rb8 80c51 internal bus write to sbuf sbuf zero detector txd p1.0 alt output function tx control s tx clock start q cl d serial port interrupt shift send load sbuf ti input shift register start ri load sbuf shift rx clock 1ffh rx control sbuf read sbuf rxd p1.1 alt input function 80c51 internal bus data tb8 16 16 2 timer 1 overflow smod1 = 0 smod1 = 1 1-to-0 transition detector figure 35. serial port mode 3
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 49 automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are adon't careo. the saden mask can be logically anded with the saddr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are treated as don't-cares. in most cases, interpreting the don't-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr and saden are loaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard uart drivers which do not make use of this feature. watchdog timer when enabled via the wdte configuration bit, the watchdog timer is operated from an independent, fully on-chip oscillator in order to provide the greatest possible dependability. when the watchdog feature is enabled, the timer must be fed regularly by software in order to prevent it from resetting the cpu, and it cannot be turned off. when disabled as a watchdog timer (via the wdte bit in the ucfg1 configuration register), it may be used as an interval timer and may generate an interrupt. the watchdog timer is shown in figure 36. the watchdog timeout time is selectable from one of eight values, nominal times range from 16 milliseconds to 2.1 seconds. the frequency tolerance of the independent watchdog rc oscillator is 37%. the timeout selections and other control bits are shown in figure 37. when the watchdog function is enabled, the wdcon register may be written once during chip initialization in order to set the watchdog timeout time. the recommended method of initializing the wdcon register is to first feed the watchdog, then write to wdcon to configure the wds20 bits. using this method, the watchdog initialization may be done any time within 10 milliseconds after startup without a watchdog overflow occurring before the initialization can be completed. since the watchdog timer oscillator is fully on-chip and independent of any external oscillator circuit used by the cpu, it intrinsically serves as an oscillator fail detection function. if the watchdog feature is enabled and the cpu oscillator fails for any reason, the watchdog timer will time out and reset the cpu. when the watchdog function is enabled, the timer is deactivated temporarily when a chip reset occurs from another source, such as a power on reset, brownout reset, or external reset. watchdog feed sequence if the watchdog timer is running, it must be fed before it times out in order to prevent a chip reset from occurring. the watchdog feed sequence consists of first writing the value 1eh, then the value e1h to the wdrst register. an example of a watchdog feed sequence is shown below. wdfeed: mov wdrst,#1eh ; first part of watchdog feed sequence. mov wdrst,#0e1h ; second part of watchdog feed sequence. the two writes to wdrst do not have to occur in consecutive instructions. an incorrect watchdog feed sequence does not cause any immediate response from the watchdog timer, which will still time out at the originally scheduled time if a correct feed sequence does not occur prior to that time. after a chip reset, the user program has a limited time in which to either feed the watchdog timer or change the timeout period. when a low cpu clock frequency is used in the application, the number of instructions that can be executed before the watchdog overflows may be quite small. watchdog reset if a watchdog reset occurs, the internal reset is active for approximately one microsecond. if the cpu clock was still running, code execution will begin immediately after that. if the processor was in power down mode, the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 50 su01635 watchdog interrupt s q 20-bit counter state clock wdte (ucfg1.7) bof (pcon.5) pof (pcon.4) watchdog reset clear 8 msbs 8 to 1 mux watchdog feed detect wdovf (wdcon.5) wds20 (wdcon.20) wdte + wdrun wdclk * wdte 500 khz rc oscillator enable clock out r figure 36. block diagram of the watchdog timer bit symbol function wdcon.7, 6 e reserved for future use. should not be set to 1 by user programs. wdcon.5 wdovf watchdog timer overflow flag. set when a watchdog reset or timer overflow occurs. cleared when the watchdog is fed. wdcon.4 wdrun watchdog run control. the watchdog timer is started when wdrun = 1 and stopped when wdrun = 0. this bit is forced to 1 (watchdog running) if the wdte configuration bit = 1. wdcon.3 wdclk watchdog clock select. the watchdog timer is clocked by cpu clock/6 when wdclk = 1 and by the watchdog rc oscillator when wdclk = 0. this bit is forced to 0 (using the watchdog rc oscillator) if the wdte configuration bit = 1. wdcon.20 wds20 watchdog rate select. wds20 timeout clocks minimum time nominal time maximum time 0 0 0 8,192 10 ms 16 ms 23 ms 0 0 1 16,384 20 ms 32 ms 45 ms 0 1 0 32,768 41 ms 65 ms 90 ms 0 1 1 65,536 82 ms 131 ms 180 ms 1 0 0 131,072 165 ms 262 ms 360 ms 1 0 1 262,144 330 ms 524 ms 719 ms 1 1 0 524,288 660 ms 1.05 sec 1.44 sec 1 1 1 1,048,576 1.3 sec 2.1 sec 2.9 sec wds0 su01183 wds1 wds2 wdclk wdrun wdovf e e 0 1 2 3 4 5 6 7 wdcon reset value: 30h for a watchdog reset. 10h for other rest sources if the watchdog is enabled via the wdte configuration bit. 00h for other reset sources if the watchdog is disabled via the wdte configuration bit. not bit addressable address: a7h figure 37. watchdog timer control register (wdcon)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 51 additional features the auxr1 register contains several special purpose control bits that relate to several chip features. auxr1 is described in figure 38. software reset the srst bit in auxr1 allows software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. if a value is written to auxr1 that contains a 1 at bit position 3, all sfrs will be initialized and execution will resume at program address 0000. care should be taken when writing to auxr1 to avoid accidental software resets. dual data pointers the dual data pointer (dptr) adds to the ways in which the processor can specify the address used with certain instructions. the dps bit in the auxr1 register selects one of the two data pointers. the dptr that is not currently selected is not accessible to software unless the dps bit is toggled. specific instructions affected by the data pointer selection are: ? inc dptr increments the data pointer by 1. ? jmp @a+dptr jump indirect relative to dptr value. ? mov dptr, #data16 load the data pointer with a 16-bit constant. ? movc a, @a+dptr move code byte relative to dptr to the accumulator. ? movx a, @dptr move data byte the accumulator to data memory relative to dptr. ? movx @dptr, a move data byte from data memory relative to dptr to the accumulator. also, any instruction that reads or manipulates the dph and dpl registers (the upper and lower bytes of the current dptr) will be affected by the setting of dps. the movx instructions have limited application for the P87LPC768 since the part does not have an external data bus. however, they may be used to access eprom configuration information (see eprom characteristics section). bit 2 of auxr1 is permanently wired as a logic 0. this is so that the dps bit may be toggled (thereby switching data pointers) simply by incrementing the auxr1 register, without the possibility of inadvertently altering other bits in the register. bit symbol function auxr1.7 kbf keyboard interrupt flag. set when any pin of port 0 that is enabled for the keyboard interrupt function goes low. must be cleared by software. auxr1.6 bod brown out disable. when set, turns off brownout detection and saves power. see power monitoring functions section for details. auxr1.5 boi brown out interrupt. when set, prevents brownout detection from causing a chip reset and allows the brownout detect function to be used as an interrupt. see the power monitoring functions section for details. auxr1.4 lpep low power eprom control bit. allows power savings in low voltage systems. set by software. can only be cleared by power-on or brownout reset. see the power reduction modes section for details. auxr1.3 srst software reset. when set by software, resets the P87LPC768 as if a hardware reset occurred. auxr1.2 e this bit contains a hard-wired 0. allows toggling of the dps bit by incrementing auxr1, without interfering with other bits in the register. auxr1.1 e reserved for future use. should not be set to 1 by user programs. auxr1.0 dps data pointer select. chooses one of two data pointers for use by the program. see text for details. dps su01637 e 0 srst lpep boi bod kbf 0 1 2 3 4 5 6 7 auxr1 reset value: 00h not bit addressable address: a2h figure 38. auxr1 register
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 52 eprom characteristics programming of the eprom on the P87LPC768 is accomplished with a serial programming method. commands, addresses, and data are transmitted to and from the device on two pins after programming mode is entered. serial programming allows easy implementation of in-circuit programming of the P87LPC768 in an application board. details of in-system programming can be found in application note an466. the P87LPC768 contains three signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes designate the device as an P87LPC768 manufactured by philips. the signature bytes may be read by the user program at addresses fc30h, fc31h and fc60h with the movc instruction, using the dptr register for addressing. a special user data area is also available for access via the movc instruction at addresses fce0h through fcffh. this acustomer codeo space is programmed in the same manner as the main code eprom and may be used to store a serial number, manufacturing date, or other application information. 32-byte customer code space a small supplemental eprom space is reserved for use by the customer in order to identify code revisions, store checksums, add a serial number to each device, or any other desired use. this area exists in the code memory space from addresses fce0h through fcffh. code execution from this space is not supported, but it may be read as data through the use of the movc instruction with the appropriate addresses. the memory may be programmed at the same time as the rest of the code memory and ucfg bytes are programmed. system configuration bytes a number of user configurable features of the P87LPC768 must be defined at power up and therefore cannot be set by the program after start of execution. those features are configured through the use of two eprom bytes that are programmed in the same manner as the eprom program space. the contents of the two configuration bytes, ucfg1 and ucfg2, are shown in figures 39 and 40. the values of these bytes may be read by the program through the use of the movx instruction at the addresses shown in the figure. bit symbol function ucfg1.7 wdte watchdog timer enable. when programmed (0), disables the watchdog timer. the timer may still be used to generate an interrupt. ucfg1.6 rpd reset pin disable. when 1 disables the reset function of pin p1.5, allowing it to be used as an input only port pin. ucfg1.5 prhi port reset high. when 1, ports reset to a high state. when 0, ports reset to a low state. ucfg1.4 bov brownout voltage select. when 1, the brownout detect voltage is 2.5v. when 0, the brownout detect voltage is 3.8v. this is described in the power monitoring functions section. ucfg1.3 clkr clock rate select. when 0, the cpu clock rate is divided by 2. this results in machine cycles taking 12 cpu clocks to complete as in the standard 80c51. for full backward compatibility, this division applies to peripheral timing as well. ucfg1.20 fosc2fsoc0 cpu oscillator type select. see oscillator section for additional information. combinations other than those shown below should not be used. they are reserved for future use. fosc2fosc0 oscillator configuration 1 1 1 external clock input on x1 (default setting for an unprogrammed part). 0 1 1 internal rc oscillator, 6 mhz 25%. 0 1 0 low frequency crystal, 20 khz to 100 khz. 0 0 1 medium frequency crystal or resonator, 100 khz to 4 mhz. 0 0 0 high frequency crystal or resonator, 4 mhz to 20 mhz. fosc0 su01185 fosc1 fosc2 clkr bov prhi rpd wdte 0 1 2 3 4 5 6 7 ucfg1 unprogrammed value: ffh address: fd00h figure 39. eprom system configuration byte 1 (ucfg1)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 53 bit symbol function ucfg2.7, 6 sb2, sb1 eprom security bits. see table entitled, aeprom security bitso for details. ucfg2.50 e reserved for future use. e su01186 e e e e e sb1 sb2 0 1 2 3 4 5 6 7 ucfg2 unprogrammed value: ffh address: fd01h figure 40. eprom system configuration byte 2 (ucfg2) security bits when neither of the security bits are programmed, the code in the eprom can be verified. when only security bit 1 is programmed , all further programming of the eprom is disabled. at that point, only security bit 2 may still be programmed. when both security bits are p rogrammed, eprom verify is also disabled. table 12. eprom security bits sb2 sb1 protection description 1 1 both security bits unprogrammed. no program security features enabled. eprom is programmable and verifiable. 1 0 only security bit 1 programmed. further eprom programming is disabled. security bit 2 may still be programmed. 0 1 only security bit 2 programmed. this combination is not supported. 0 0 both security bits programmed. all eprom verification and programming are disabled. absolute maximum ratings parameter rating unit operating temperature under bias 55 to +125 c storage temperature range 65 to +150 c voltage on rst /v pp pin to v ss 0 to +11.0 v voltage on any other pin to v ss 0.5 to v dd +0.5v v maximum i ol per i/o pin 20 ma power dissipation (based on package heat transfer, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification are not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to vss unless otherwise noted.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 54 dc electrical characteristics v dd = 2.7 v to 6.0 v unless otherwise specified; t amb = 0 c to +70 c or 40 c to +85 c, unless otherwise specified. symbol parameter test conditions limits unit symbol parameter test conditions min typ 1,2 max unit i power su pp ly current o p erating 5.0 v, 20 mhz 11 15 25 ma i dd po w er s u ppl y c u rrent , operating 3.0 v, 10 mhz 11 4 7 ma i power su pp ly current idle mode 5.0 v, 20 mhz 11 6 10 ma i id po w er s u ppl y c u rrent , idle mode 3.0 v, 10 mhz 11 2 4 ma i power su pp ly current power down mode 5.0 v 11 1 10 m a i pd po w er s u ppl y c u rrent , po w er do w n mode 3.0 v 11 1 5 m a v ram ram keep-alive voltage 1.5 v v in p ut low voltage (ttl in p ut) 4.0 v < v dd < 6.0 v 0.5 0.2 v dd 0.1 v v il inp u t lo w v oltage (ttl inp u t) 2.7 v < v dd < 4.0 v 0.5 0.7 v v il1 negative going threshold (schmitt input) 0.5 v dd 0.4 v dd 0.3 v dd v v ih input high voltage (ttl input) 0.2 v dd +0.9 v dd +0.5 v v ih1 positive going threshold (schmitt input) 0.7 v dd 0.6 v dd v dd +0.5 v hys hysteresis voltage 0.2 v dd v v ol output low voltage all ports 5, 9 i ol = 3.2 ma, v dd = 2.7 v 0.4 v v ol1 output low voltage all ports 5, 9 i ol = 20 ma, v dd = 2.7 v 1.0 v v o out p ut high voltage all p orts 3 i oh = 20 m a, v dd = 2.7 v v dd 0.7 v v oh o u tp u t high v oltage , all ports 3 i oh = 30 m a, v dd = 4.5 v v dd 0.7 v v oh1 output high voltage, all ports 4 i oh = 1.0 ma, v dd = 2.7 v v dd 0.7 v c io input/output pin capacitance 10 15 pf i il logical 0 input current, all ports 8 v in = 0.4 v 50 m a i li input leakage current, all ports 7 v in = v il or v ih 2 m a i logical 1 to 0 transition current all p orts 3, 6 v in = 1.5 v at v dd = 3.0 v 30 250 m a i tl logical 1 to 0 transition c u rrent , all ports 3 , 6 v in = 2.0 v at v dd = 5.5 v 150 650 m a r rst internal reset pull-up resistor 40 225 k w v bo2.5 brownout trip voltage with bov = 1 12 t amb = 0 c to +70 c 2.45 2.5 2.65 v v bo3.8 brownout trip voltage with bov = 0 3.45 3.8 3.90 v v ref bandgap reference voltage 1.11 1.26 1.41 v notes: 1. typical ratings are not guaranteed. the values listed are at room temperature, 5 v. 2. see other figures for details. 3. ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). does not apply to open drain pi ns. 4. ports in push-pull mode. does not apply to open drain pins. 5. in all output modes except high impedance mode. 6. port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. this current i s highest when v in is approximately 2 v. 7. measured with port in high impedance mode. parameter is guaranteed but not tested at cold temperature. 8. measured with port in quasi-bidirectional mode. 9. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 20 ma maximum total i ol for all outputs: 80 ma maximum total i oh for all outputs: 5 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 10. pin capacitance is characterized but not tested. 11. the i dd , i id , and i pd specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer. for v dd = 3 v, lpep = 1. refer to the appropriate figures on the following pages for additional current drawn by each of these functions and detailed graphs for other frequency and voltage combinations. 12. devices initially operating at v dd = 2.7v or above and at f osc = 10 mhz or less are guaranteed to continue to execute instructions correctly at the brownout trip point. initial power-on operation below v dd = 2.7 v is not guaranteed. comparator electrical characteristics v dd = 3.0 v to 6.0 v unless otherwise specified; t amb = 0 c to +70 c or 40 c to +85 c, unless otherwise specified
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 55 symbol parameter test conditions limits unit symbol parameter test conditions min typ max unit v io offset voltage comparator inputs 1 10 mv v cr common mode range comparator inputs 0 v dd 0.3 v cmrr common mode rejection ratio 1 50 db response time 250 500 ns comparator enable to output valid 10 m s i il input leakage current, comparator 0 < v in < v dd 10 m a note: 1. this parameter is guaranteed by characterization, but not tested in production. a/d converter dc electrical characteristics vdd = 3.0v to 6.0v unless otherwise specified; tamb = 0 to +70 c for commercial, -40 c to +85 c for industrial, unless otherwise specified. symbol parameter test conditions limits unit symbol parameter test conditions min max unit av in analog input voltage v ss - 0.2 v dd + 0.2 v r ref resistance between v dd and v ss a/d enabled tbd tbd k w c ia analog input capacitance 15 pf dl e differential non-linearity 1,2,3 1 lsb il e integral non-linearity 1,4 1 lsb os e offset error 1,5 2 lsb g e gain error 1,6 1 % a e absolute voltage error 1,7 1 lsb m ctc channel-to-channel matching 1 lsb c t crosstalk between inputs of port 8 0 - 100khz -60 db - input slew rate 100 v/ms - input source impedance 10 k w notes: 1. conditions: v ss = 0v; v dd = 5.12v. 2. the a/d is monotonic, there are no missing codes 3. the differential non-linearity (dl e ) is the difference between the actual step width and the ideal step width. see figure 41. 4. the integral non-linearity (il e ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 41. 5. the offset error (os e ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and the straight line which fits the ideal transfer curve. see figure 41. 6. the gain error (g e ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset erro r), and the straight line which fits the ideal transfer curve. gain error is constant at every point on the transfer curve. see fig ure 41. 7. the absolute voltage error (a e ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. 8. this should be considered when both analog and digital signals are input simultaneously to a/d pins. 9. changing the input voltage faster than this may cause erroneous readings. 10. a source impedance higher than this driving an a/d input may result in loss of precision and erroneous readings.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 56 255 254 253 252 251 (2) (1) 256 250 251 252 253 254 255 7 123456 7 6 5 4 3 2 1 0 250 (5) (4) (3) 1 lsb (ideal) code out offset error os e gain error g e av in (lsb ideal ) offset error os e v dd - v ss 1 lsb = 256 (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential non-linearity (dl e ). (4) integral non-linearity (il e ). (5) center of a step of the actual transfer curve. su01355 figure 41. a/d conversion characteristics
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 57 ac electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c, v dd = 2.7 v to 6.0 v unless otherwise specified, v ss = 0 v 1, 2, 3 symbol figure parameter limits unit symbol figure parameter min max unit external clock f c 43 oscillator frequency (v dd = 4.5 v to 6.0 v) 0 20 mhz f c 43 oscillator frequency (v dd = 2.7 v to 6.0 v) 0 10 mhz t c 43 clock period and cpu timing cycle 1/f c ns t chcx 43 clock high-time 4 20 ns t clcx 43 clock low time 4 20 ns shift register t xlxl 42 serial port clock cycle time 6t c ns t qvxh 42 output data setup to clock rising edge 5t c 133 ns t xhqx 42 output data hold after clock rising edge 1t c 80 ns t xhdv 42 input data setup to clock rising edge 5t c 133 ns t xhdx 42 input data hold after clock rising edge 0 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for all outputs = 80 pf. 3. parts are guaranteed to operate down to 0 hz. 4. applies only to an external clock source, not when a crystal is connected to the x1 and x2 pins.
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 58 clear ri t xlxl clock t xhqx t qvxh output data write to sbuf input data t xhdv t xhdx set ti set ri su01187 7 123456 0 valid valid valid valid valid valid valid valid figure 42. shift register mode timing su01188 v dd 0.5 0.45v 0.2v dd + 0.9 0.2 v dd 0.1 t chcl t clch t chcx t clcx t c figure 43. external clock timing su01202 100 10 1 10 100 idd (ua) frequency (khz) 6.0 v 5.0 v 4.0 v 3.3 v 2.7 v figure 44. typical low frequency oscillator idd at 25 c (see note 1) su01203 1000 100 10 100 10,000 idd (ua) frequency (khz) 1,000 6.0 v 5.0 v 2.7 v 6.0 v 5.0 v 4.0 v 3.3 v 2.7 v figure 45. typical medium frequency oscillator idd at 25 c (see note 1)
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 59 su01204 10,000 1,000 100 1 100 idd (ua) frequency (mhz) 10 6.0 v 5.0 v 4.0 v 3.3 v 2.7 v figure 46. typical high frequency oscillator idd versus frequency at 25 c (see note 1) su01205 100,000 100 10 10 100,000 idd (ua) frequency (khz) 1,000 10,000 6.0 v 5.0 v 4.0 v 3.3 v 2.7 v 100 1,000 10,000 figure 47. typical active idd versus frequency (external clock, 25 c, lpep=0) su01206 10,000 100 1 10 10,000 idd (ua) frequency (khz) 4.0 v 3.3 v 2.7 v 100 1,000 1,000 10 figure 48. typical active idd versus frequency (external clock, 25 c, lpep=1) su01207 100 10 1 10 100 idd (ua) frequency (khz) 4.0 v 3.3 v 2.7 v 1,000 10,000 1,000 10,000 figure 49. typical idle idd versus frequency (external clock, 25 c, lpep=1) su01208 10,000 1,000 10 10 100,000 idd (ua) frequency (khz) 100 1,000 10,000 100 6.0 v 5.0 v 4.0 v 3.3 v 2.7 v figure 50. typical idle idd versus frequency (external clock, 25 c, lpep=0) note: 1. total idd at sum of oscillator current and active or idle current shown in figures 47, 48, 49 or 50 as appropriate
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 60 dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 61 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 62 revision history date cpcn description 2002 mar 12 9397 750 09558 added revision history updated reset section 2001 aug 06 9397 750 08661 previous release
philips semiconductors preliminary data P87LPC768 low power, low price, low pin count (20 pin) microcontroller with 4 kb otp 8-bit a/d, pulse width modulator 2002 mar 12 63 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2002 all rights reserved. printed in u.s.a. date of release: 03-02 document order number: 9397 750 09558

data sheet status [1] objective data preliminary data product data product status [2] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change notification (cpcn) procedure snw-sq-650a. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com.

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